DE3381128D1 - Verfahren zur herstellung einer isolationszone. - Google Patents
Verfahren zur herstellung einer isolationszone.Info
- Publication number
- DE3381128D1 DE3381128D1 DE8383307091T DE3381128T DE3381128D1 DE 3381128 D1 DE3381128 D1 DE 3381128D1 DE 8383307091 T DE8383307091 T DE 8383307091T DE 3381128 T DE3381128 T DE 3381128T DE 3381128 D1 DE3381128 D1 DE 3381128D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- insulation zone
- insulation
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57209173A JPS5999738A (ja) | 1982-11-29 | 1982-11-29 | 半導体装置の製造方法 |
JP57209172A JPS5999737A (ja) | 1982-11-29 | 1982-11-29 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3381128D1 true DE3381128D1 (de) | 1990-02-22 |
Family
ID=26517270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383307091T Expired - Fee Related DE3381128D1 (de) | 1982-11-29 | 1983-11-21 | Verfahren zur herstellung einer isolationszone. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4465532A (de) |
EP (1) | EP0113517B1 (de) |
KR (1) | KR860001056B1 (de) |
CA (1) | CA1204525A (de) |
DE (1) | DE3381128D1 (de) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4570325A (en) * | 1983-12-16 | 1986-02-18 | Kabushiki Kaisha Toshiba | Manufacturing a field oxide region for a semiconductor device |
GB8406432D0 (en) * | 1984-03-12 | 1984-04-18 | British Telecomm | Semiconductor devices |
FR2610140B1 (fr) * | 1987-01-26 | 1990-04-20 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de ses zones d'isolation electrique |
US4799990A (en) * | 1987-04-30 | 1989-01-24 | Ibm Corporation | Method of self-aligning a trench isolation structure to an implanted well region |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5338398A (en) * | 1991-03-28 | 1994-08-16 | Applied Materials, Inc. | Tungsten silicide etch process selective to photoresist and oxide |
US5248625A (en) | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
DE4219592C2 (de) * | 1991-06-17 | 2001-12-06 | Gold Star Electronics | Verfahren zur Ausbildung eines Graben-Isolationsbereichs mittels einer Reaktionsschicht |
FR2683944B1 (fr) * | 1991-11-14 | 1994-02-18 | Sgs Thomson Microelectronics Sa | Procede de gravure d'un sillon profond. |
US5354706A (en) * | 1993-03-02 | 1994-10-11 | Lsi Logic Corporation | Formation of uniform dimension conductive lines on a semiconductor wafer |
US5356828A (en) * | 1993-07-01 | 1994-10-18 | Digital Equipment Corporation | Method of forming micro-trench isolation regions in the fabrication of semiconductor devices |
JPH07193121A (ja) * | 1993-12-27 | 1995-07-28 | Toshiba Corp | 半導体装置の製造方法 |
US5880033A (en) * | 1996-06-17 | 1999-03-09 | Applied Materials, Inc. | Method for etching metal silicide with high selectivity to polysilicon |
JP3058112B2 (ja) * | 1997-02-27 | 2000-07-04 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US6872322B1 (en) | 1997-11-12 | 2005-03-29 | Applied Materials, Inc. | Multiple stage process for cleaning process chambers |
US6136211A (en) * | 1997-11-12 | 2000-10-24 | Applied Materials, Inc. | Self-cleaning etch process |
US6797188B1 (en) | 1997-11-12 | 2004-09-28 | Meihua Shen | Self-cleaning process for etching silicon-containing material |
US6322714B1 (en) | 1997-11-12 | 2001-11-27 | Applied Materials Inc. | Process for etching silicon-containing material on substrates |
US6527968B1 (en) | 2000-03-27 | 2003-03-04 | Applied Materials Inc. | Two-stage self-cleaning silicon etch process |
US6905800B1 (en) | 2000-11-21 | 2005-06-14 | Stephen Yuen | Etching a substrate in a process zone |
US6852242B2 (en) | 2001-02-23 | 2005-02-08 | Zhi-Wen Sun | Cleaning of multicompositional etchant residues |
KR100792409B1 (ko) * | 2004-10-12 | 2008-01-09 | 주식회사 하이닉스반도체 | 텅스텐막을 희생 하드마스크로 이용하는 반도체소자 제조방법 |
US8118946B2 (en) | 2007-11-30 | 2012-02-21 | Wesley George Lau | Cleaning process residues from substrate processing chamber components |
US8263502B2 (en) * | 2008-08-13 | 2012-09-11 | Synos Technology, Inc. | Forming substrate structure by filling recesses with deposition material |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2251823A1 (de) * | 1972-10-21 | 1974-05-02 | Itt Ind Gmbh Deutsche | Halbleiterelement und herstellungsverfahren |
US4282647A (en) * | 1978-04-04 | 1981-08-11 | Standard Microsystems Corporation | Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask |
JPS5636143A (en) * | 1979-08-31 | 1981-04-09 | Hitachi Ltd | Manufacture of semiconductor device |
DE3023410A1 (de) * | 1980-06-23 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von mos-strukturen |
US4333965A (en) * | 1980-09-15 | 1982-06-08 | General Electric Company | Method of making integrated circuits |
US4373990A (en) * | 1981-01-08 | 1983-02-15 | Bell Telephone Laboratories, Incorporated | Dry etching aluminum |
JPS5848936A (ja) * | 1981-09-10 | 1983-03-23 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS5864044A (ja) * | 1981-10-14 | 1983-04-16 | Toshiba Corp | 半導体装置の製造方法 |
US4390393A (en) * | 1981-11-12 | 1983-06-28 | General Electric Company | Method of forming an isolation trench in a semiconductor substrate |
US4422897A (en) * | 1982-05-25 | 1983-12-27 | Massachusetts Institute Of Technology | Process for selectively etching silicon |
-
1983
- 1983-11-04 CA CA000440422A patent/CA1204525A/en not_active Expired
- 1983-11-07 US US06/549,470 patent/US4465532A/en not_active Expired - Fee Related
- 1983-11-14 KR KR1019830005396A patent/KR860001056B1/ko not_active IP Right Cessation
- 1983-11-21 DE DE8383307091T patent/DE3381128D1/de not_active Expired - Fee Related
- 1983-11-21 EP EP83307091A patent/EP0113517B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA1204525A (en) | 1986-05-13 |
KR840006729A (ko) | 1984-12-01 |
EP0113517A2 (de) | 1984-07-18 |
KR860001056B1 (ko) | 1986-08-01 |
EP0113517B1 (de) | 1990-01-17 |
EP0113517A3 (en) | 1986-06-11 |
US4465532A (en) | 1984-08-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |