WO2001026193A1

WO2001026193A1 - Method for making a ridge waveguide semiconductor device

Info

Publication number: WO2001026193A1
Application number: PCT/US2000/027041
Authority: WO
Inventors: Yi Qian; Hanh Lu
Original assignee: Corning Lasertron, Inc.
Priority date: 1999-10-01
Filing date: 2000-09-29
Publication date: 2001-04-12
Also published as: TW471065B; AU7743900A

Abstract

An electro-optical device including a ridge waveguide with at least one overhanging sidewall has polyimide filling in the region under the overhanging sidewall to facilitate the deposition of a continuous metal ridge-contact layer. The polyimide is deposited surrounding the ridge waveguide and etched using directed reactive ion etching at low pressure and high temperature leaving polyimide filling in the region under the overhanging sidewall.

Description

METHOD FOR MAKING A RIDGE WAVEGUIDE SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION

In ridge-waveguide, electro-optical devices, the spatial mode confinement of a generated optical signal is dependent, to varying degrees, on the width of the bottom of the ridge-waveguide. To generate the optical signal, a current is injected through a metal layer in contact with the top of the ridge-waveguide. The area on top of the ridge waveguide structure in the electro-optical device must provide sufficient contact area to control resistance, so that heat generation can be minimized. The injection current is transmitted into the top and then the bottom of the ridge- waveguide toward the active layer of the electro-optical device. Therefore, the width of the top of the ridge-waveguide is dependent on the contact area required for injection of current and the width of the bottom of the ridge- waveguide is driven typically by the necessity of a single spatial mode operation. For example, in a single mode 1500 nanometers (nm) electro-optical device the bottom of the ridge- waveguide is about 2 micrometers (μm) and the top of the ridge waveguide is preferred to have a wider width (i.e., 4μm) to reduce the device resistance.

Ridge waveguides with tops wider than bases have overhanging sidewalls. The overhanging sidewalls make it difficult to deposit the metal layer to provide the connection to the top of the ridge- waveguide because discontinuities may occur at the bottom corner under the overhanging sidewalls since most metal deposition techniques tend to be directional. In two channel electro-optical devices where the ridge is defined by longitudinal trenches on either side of the ridge, the overhanging sidewalls extend over the channels located at the sides of the ridge- waveguide. Existing techniques planarize the surface aήer filling the trenches completely with an organic filling material. On such technique is described in United States Patent

Number 4.654.120. entitled "Method of Making a Planar Trench Semiconductor Structure" by James J. Dougherty. The channels are filled completely with a filling material, such as an organic material then the deposited organic material is etched so as to form a planar surface. The metal layer is deposited on top of the planar surface.

This method requires very thick organic material and very precise photolithography in order to form the planar surface. Also, filling the channels completely with the organic material results in bad thermal dissipation and may cause stress problems as a result of the different stress coefficients between the organic filling material, the metal layer, and the semiconductor materials.

SUMMARY OF THE INVENTION

The present invention is directed to an electro-optical device and a method for its fabrication. The electro-optical device includes a ridge waveguide. An overhung region under the sidewalls occurs typically as a result of the width of the top of the ridge- waveguide being greater than the width of the bottom of the ridge- waveguide. The invention utilizes an organic filling material, such as polyimide, to fill the ridge waveguide's overhung region. A continuous metal layer is then deposited on top off the organic filling material and the top of the ridge waveguide.

Depending on the implementation, the ridge-waveguide has a reverse mesa, top hat mesa, or mushroom mesa cross-section.

The ridge-waveguide is formed with at least one overhanging sidewall. An organic filling material is deposited surrounding the ridge. The organic material such as polyimide is etched using a directed reactive ion etching technique at low pressure and high voltage to create the straight wall surrounding the ridge waveguide. The etching process etches below the top of the ridge- waveguide to remove the polyimide from the top. After the etching step is complete, polyimide remains in the overhung regions of the ridge- waveguide. The metal layer is deposited on the top of the ridge-waveguide and the remaining polyimide layer in the overhung regions.

The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Of the drawings:

Fig. 1A is a schematic, cross-sectional view of an electro-optical device including a two-channel ridge- waveguide according to the present invention;

Fig. IB is an image of a cross-sectional view of an electro-optical device including a two-channel ridge-waveguide according to the present invention;

Fig. 1C is another image of a cross-sectional view of an electro-optical device including a two-channel ridge-waveguide according to the present invention; Fig. 2 is a schematic, cross-sectional view of the ridge- waveguide during fabrication after the ridge etch;

Fig. 3 is a schematic, cross-sectional view of the electro-optical device after the deposition of the silicon oxide passivation layer;

Fig. 4 is a schematic, cross-sectional view of the electro-optical device after the deposition of the polyimide layer;

Fig. 5A is a schematic, cross-sectional view showing one result after etching the polyimide layer; Fig. 5B is a schematic, cross-sectional view showing another result after etching the polyimide layer;

Fig. 6 is a schematic, cross-sectional view of the electro-optical device after the deposition of a silicon oxide interlayer; Fig. 7 is a schematic, cross-sectional view of the electro-optical device before etching the silicon oxide layers;

Fig. 8 is a schematic, cross-sectional view of the electro-optical device after the silicon oxide layers have been etched off the top of the ridge-waveguide;

Fig. 9A is a schematic, cross-sectional view showing another ridge - waveguide configuration in which the present invention is used in one embodiment;

Fig. 9B is a schematic, cross-sectional view showing yet another ridge- waveguide configuration in which the present invention is used in another embodiment;

Fig. 10 is a schematic, cross-sectional view showing an electro-optical device including a ridge-waveguide with no channels according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Fig. 1A shows a two channel ridge-waveguide electro-optical device 10, which has been constructed according to the principles of the present invention.

The substrate material 100 is preferably indium phosphide InP. A preferably indium aluminum gallium arsenide InAlGaAs or indium gallium arsenide phosphide InGaAsP epitaxial active layer 102 provides the electro-optical characteristics of the device. A ridge waveguide 112 is formed above the active layer 102. The ridge waveguide 112 is preferably made of indium phosphide InP. The ridge waveguide 112 is formed such that the width of the top of the ridge waveguide ("W_t") 1 14 is greater than the width of the bottom of the ridge waveguide ("W_b") 1 16. W_t 1 14 and W_b 116 can differ by more than 2μm and the height of the ridge- waveguide is greater than 2μm. For a device operating at 1500nm, W, = 4μm and W_b = 2μm. The etch stop layer 104 (preferably InGaAsP) serves a stop to the wet chemical etching of the ridge waveguide 1 12.

In the preferred embodiment, the ridge waveguide 112 is a reverse mesa cross-section as shown.

A silicon oxide passivation layer 106 covers the side walls of the ridge- waveguide 112 and tops other than the top of the ridge- waveguide 112. A polyimide layer 110 A, B covers the silicon oxide passivation layer 106 on the sidewalls of the ridge waveguide 112. The polyimide layer 110 A, B fills at least the region under the overhang 132 of the side walls of the ridge- waveguide 112.

There is a silicon oxide interlayer 130 deposited on the straight sidewall created by the polyimide and on top of the portion of the silicon oxide passivation layer 106 not covered by the polyimide layer 110 A, B.

A p-metal contact layer 108 is formed over the silicon oxide interlayer 130 and the polyimide layer 110A, B with an ohmic contact to the top of the ridge- waveguide 112. In a preferred embodiment, the contact layer 108 is a tri-metal of titanium, platinum, and gold. A large bond pad 124, 128 of gold is then formed on the contact layer 108, adjacent to the ridge waveguide 112, to receive a wire 126, with a wire ball 126 A formed on the pad 124, preferably by ultrasonic wire bonding. A ridge injection current from wire 126 is conducted down through the ridge waveguide 112 through the active layer 102 by the p-metal contact layer 108.

Figs. 1A and IB are images of two-channel ridge-waveguide devices 10, constructed according to the principles of the present invention.

Figs. 2 through 8 illustrate the process for manufacturing the inventive ridge- waveguide electro-optical device 10. Fig. 2 is a cross-sectional view of the ridge- waveguide 112 during fabrication after the ridge- waveguide 112 is formed by etching the InP layer. Specifically, in the illustrated embodiment, the ridge 112 is formed by creating two channels 138a, 138b etched into the substrate in the phosphide layer to create a lateral optical confinement and to thereby define the ridge 112. In the present implementation, the channels are not etched down to the layer to the active in this weakly-guided implementation. On the other hand, the ridge etch process stops at the etch stop layer 104. The invention also has applicability to buried heterostructured configurations, however. Further, the invention also applies to embodiments where the substrate is completely etched away on either side of the ridge. The ridge- waveguide 112 is a reverse mesa configuration with W_t 114 greater than W_b 116. The reverse mesa configuration results in an overhang 132.

Fig. 3 is a cross-sectional view of the electro-optical device after the deposition of the silicon oxide passivation layer 106. The silicon oxide passivation layer 106 is deposited on the top and sidewalls of the ridge- waveguide 112 to improve adhesion between the InP layer and the polyimide layer 110. The silicon oxide passivation layer 106 is about 3000 A thick.

Fig. 4 is a cross-sectional view of the electro-optical device after the deposition of the polyimide layer 110. The depth of the polyimide layer 110 is dependent on the height of the ridge-waveguide 1 12. For example, for a 1.8 μm high ridge- waveguide the depth of the layer of polyimide deposited is approximately 2μm. The polyimide may be deposited using a standard polyimide spinning technique followed by a curing technique in a thermal furnace (135^°C at 30 minuutes; 350^°C at 30 minutes; 400^°C at 30 minutes; and 450^°C at 10 minutes, preferably). The step of curing may result in depressions or grooves 136A, B over the channels. Sometimes, these grooves may already exist before curing. The grooves do not have to be removed because the step of depositing does not need to planarize the surface of the polyimide. After deposition, the polyimide layer 110 is then etched using a Reactive Ion Etching ("RIE") 1 18 technique with oxygen (O₂ plasma) 118 as the etchant. The oxygen 118 removes the polyimide on the surface until the silicon oxide passivation layer 106 on top of the ridge-waveguide 112 is exposed. A directional etching technique is used to perform the etching step using a low pressure of less than 25 millitorrs (mT) or about 5mT and a high DC voltage of higher than 350 electron volts (eV) or about 650 eV preferably. The low pressure and high voltage reduces lateral scattering during etching because of the confinement of the electrical field resulting in a directional etching. The 650eV is higher than the 350eV typically used for RIE etching because the silicon passivation layer 106 on top of the InP protects the InP from bulk damage and allows the higher voltage to be used.

The etching step performs preferably greater than 100% over etching to remove all the polyimide from the top of the silicon oxide passivation layer 106 on the top of the ridge-waveguide 112. Over etching is necessary because any polyimide remaining on top of the silicon oxide would act as an etch mask in the later etching step to remove the silicon oxide passivation layer 106 from the top of the ridge- waveguide 112 and would then affect the conductivity of the contact to top of the ridge- waveguide 112.

The 100% over etching may be performed all the way to the silicon oxide passivation layer 106 at the bottom of the channel. For example, in the case of a

2μm ridge- waveguide the polyimide layer is over etched to a depth of 4μm to ensure that all of the polyimide is removed from the top of the ridge- waveguide.

The polyimide in the region under the overhang 132 is not etched because the overhang 132 acts as a mask for the directional RIE polyimide etch. Therefore, the etching process does not have to be precise because the silicon oxide passivation layer 106 at the bottom of the channel protects the InP layer and the overhang 132 protects the polyimide in the region under the overhang 132. Fig. 5A shows one result after the polyimide etch step is complete. As shown, all the polyimide layer 110 has been removed from the top of the ridge- waveguide 112. The polyimide regions 110A-B remaining after the etching include the region under the overhang 132 of the ridge- waveguide 1 12 and the top of the silicon passivation layer 106 along the bottom of the channels at each side of the ridge-waveguide 112. The overhang 132 provides a self-alignment technique allowing a large tolerance in control of the process.

Fig. 5B shows another result after etching the polyimide layer. The polyimide regions 110C-F remaining after the etching include the region under the overhang 132. No polyimide remains along the bottom of the channels at each side of the ridge- waveguide 112. The silicon passivation layer 106 acts as an etch stop because the oxygen does not etch silicon oxide.

The polyimide regions 110A-F in Figs. 5A-B together with the ridge waveguide form a structure to facilitate the deposition of the metal layer. The process of etching the polyimide layer 1 10 does not have to be very precise therefore a process with a high tolerance can be used because the overhang 132 acts as a natural etch stop and the amount of polyimide remaining along the bottom of the channel is not critical to the process. This makes the process very easy to control. The preferred situation is shown in Fig. 5B with polyimide remaining only in the regions under the overhang 132.

Fig. 6 is a cross-sectional view of the electro-optical device after the deposition of a silicon oxide interlayer 130. The depth of the silicon oxide o interlayer 130 is approximately 2000 A. The silicon oxide interlayer 130 is deposited on top of the polyimide layer 1 10 to provide protection. The silicon oxide interlayer is deposited on top of the silicon oxide passivation layer 106 in the areas in which the polyimide layer 110 has been removed. Fig. 7 is a cross-sectional view of the electro-optical device before etching the silicon oxide passivation layer 106 and the silicon oxide interlayer 130 using a well-known photoresist pull-back technique. A layer of photoresist 120 is deposited in regions outside the ridge-waveguide 112 to protect the areas other than the top of the ridge waveguide from being etched. This step does not need very precise alignment. All that is required is that the photoresist cover the other regions because only the silicon passivation layer 106 on the top of the ridge- waveguide is to be removed.

A RIE technique using an etchant, such as CHF₃, is used to remove the silicon oxide passivation layer 106 and the silicon dioxide interlayer 130 from the top of the ridge-waveguide 112. Since CHF₃ does not etch photoresist, the photoresist deposited on the other tops acts as a mask. After the silicon dioxide layers (the silicon dioxide passivation layer 106 and the silicon dioxide interlayer 130) have been removed from the top of the ridge waveguide, the photoresist is removed.

Fig. 8 is a cross-sectional view of the electro-optical device after the silicon oxide layers have been etched from the top of the ridge-waveguide 112. The metal layer 108 is deposited in a evaporator by sputtering. It is easy to ensure good metal coverage because the polyimide has formed a slope under the overhang 132 on top of which_the metal layer is deposited.

The ridge-waveguide configuration is not limited to the reverse mesa configuration shown, it may be one of the configurations described in conjunction with Figs. 9A and 9B or any configuration in which W_t 114 is greater than W_b 116. There is a channel 138A, B on each side of the ridge waveguide 1 12. The invention is not limited to a two channel ridge waveguide it also applies to ridge waveguides with no channels described later in conjunction with Fig. 10. Fig. 9A shows shows another ridge-waveguide configuration with W_t greater than W_b in which the present invention may be used. The configuration shown is a mushroom configuration. Here, the polyimide is deposited as shown by the dotted line to ensure continuity of subsequent contact or other conductive layers.

Fig. 9B shows yet another ridge-waveguide configuration with W_t greater than W_b in which the present invention may be used. The configuration shown is a top hat configuration. Similar to the reverse mesa configuration shown in FIG. 1 polyimide may be deposited to cover the region under the overhang in the ridge- waveguides shown in Figs. 9A-B in order to provide continuous metal coverage.

Fig. 10 shows a cross sectional view of an electro-optical device including a ridge-waveguide with no channels according to the present invention. A silicon oxide passivation layer 106 is deposited on the side walls of the ridge-waveguide 112. A polyimide layer 110 A, B is deposited on the silicon oxide passivation layer 106 on the sides of the ridge waveguide 112. The polyimide layer 110 A, B fills in at least the overhang region 132 of the ridge waveguide 112. A p-metal contact layer

108 is deposited on the silicon oxide interlayer 130 and the polyimide layer 110 A, B with an ohmic contact to the top of the ridge-waveguide 112. In a ridge-waveguide electro-optical device with no channels as shown in Fig. 10 the photoresist pull-back step is not necessary.

Generally, the present invention is applicable to any ridge-waveguide semiconductor device and opto-electronics integration including lasers, modulators, switches and amplifiers. The advantages of this technique include better stress distribution and relaxation. The bottom of the channels in a two channel ridge- waveguide electro-optical device are not filled in completely with polyimide. As a result, the thermal dissipation is better and there is less stress compared to filling the channels completely with polyimide. In addition, this technique is easy to control, which is crucial for high volume manufacturing. While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A semiconductor electro-optical device, comprising: a ridge waveguide with at least one overhanging sidewall, defining an overhung region; and an organic layer, the organic layer filling in at least under the overhung region of the sidewall to facilitate connection of a metal contact layer.

2. A semiconductor electro-optical device as claimed in Claim 1, wherein the metal layer is deposited on a top and across sidewalls of the ridge.

3. A semiconductor electro-optical device as claimed in Claim 1, wherein the ridge has a reverse mesa cross-section.

4. A semiconductor electro-optical device as claimed in Claim 1 , wherein the ridge is a mushroom mesa cross-section.

5. A semiconductor electro-optical device as claimed in Claim 1, wherein the ridge is a top hat mesa cross-section.

6. A semiconductor electro-optical device as claimed in Claim 1, wherein the electro-optical device is a modulator.

7. A semiconductor electro-optical device as claimed in Claim 1 , wherein the electro-optical device is a laser.

8. A semiconductor electro-optical device as claimed in Claim 1, wherein the electro-optical device is a switch.

9. A semiconductor electro-optical device as claimed in Claim 1, wherein the electo-optical device is an amplifier.

10. A semiconductor electro-optical device as claimed in Claim 1, wherein: the top of the ridge is wider than the bottom of the ridge and the organic layer and the ridge form a structure with sloping walls to facilitate connection of a continuous metal layer deposition on the top and the sidewalls of the structure.

11. A semiconductor electro-optical device as claimed in Claim 1 , wherein the organic layer is a polyimide layer.

12. A semiconductor electro-optical device as claimed in Claim 1, wherein the the organic layer fills in at least under the overhung region of the sidewall and below the top of the ridge.

13. A process for making an electro-optical device, the process comprising: forming a ridge waveguide with at least one overhanging sidewall; depositing an organic layer surrounding the ridge; and etching the organic layer to remove the organic layer from the top of the waveguide and leave the organic material at least under overhung regions of the sidewalls to facilitate connection of a continuous metal contact layer.

14. A process as claimed in Claim 13, wherein the step of etching is performed using reactive ion etching at a low pressure and a high voltage.

15. A process as claimed in Claim 14, wherein the pressure is less than 25mT.

16. A process as claimed in Claim 14, wherein the pressure is approximately 5mT.

17. A process as claimed in Claim 14, wherein the voltage is greater than 350eV.

18. A process as claimed in Claim 14, wherein the voltage is approximately 650eV.

19. A process as claimed in Claim 14, further comprising depositing a silicon oxide layer on top of the ridge.

20. A process as claimed in Claim 19, further comprising depositing the metal layer on the top of and across the sidewalls of the ridge.

21. A process as claimed in Claim 13, wherein the ridge has a reverse mesa cross-section.

22. A process as claimed in Claim 13, wherein the ridge is a mushroom mesa cross-section.

23. A process as claimed in Claim 13, wherein the ridge is a top hat mesa cross- section.

24. A process as claimed in Claim 13, wherein the electro-optical device is a modulator.

25. A process as claimed in Claim 13, wherein the electro-optical device is a laser.

26. A process as claimed in Claim 13, wherein the electro-optical device is a switch.

27. A process as claimed in Claim 13, wherein the electro-optical device is an amplifier.

28. A process as claimed in Claim 13, wherein the organic layer is polyimide and further comprising: depositing a silicon passivation layer on top and sidewalls of the ridge waveguide; depositing a silicon oxide layer on top of the ridge and on top of the polyimide layer; etching the top of the ridge waveguide to remove the silicon oxide layer; and depositing a metal layer on the top of the ridge and on the overhang regions of the sidewalls.

29. A process for making an electro-optical device, the process comprising: forming a ridge waveguide with at least one overhanging sidewall; depositing a silicon passivation layer on top and sidewalls of the ridge waveguide; depositing an organic layer surrounding the ridge; etching the organic layer to remove the organic layer from the top of the waveguide and leave the organic material at least under overhung regions of the sidewalls; depositing a silicon oxide layer on top of the ridge and on top of the organic layer; etching the top of the ridge waveguide to remove the silicon oxide layer; and depositing the metal layer on the top of the ridge and on the overhang regions of the sidewalls.

30. A semiconductor electro-optical device comprising: a ridge waveguide with at least one overhanging sidewall, the top of the ridge being wider than the bottom of the ridge; and an organic layer filling in at least under the overhang regions of the sidewalls, the organic layer and the ridge forming a structure with sloping walls to facilitate connection of a continuous metal layer deposition on the top and the sidewalls of the structure.

31. The semiconductor electro-optic device as claimed in Claim 30, wherein the organic layer is polyimide.

32. The semiconductor electro-optic device as claimed in Claim 30, wherein a silicon oxide passivation layer covers the side walls of the ridge waveguide.

33. The semiconductor electro-optic device as claimed in Claim 32, wherein the organic layer covers the silicon oxide passivation layer on the sidewalls of the ridge waveguide.

34. The semiconductor electro-optic device as claimed in Claim 33, wherein a silicon oxide interlayer is interposed between the organic layer and the metal layer.