JP5297892B2 - Optical semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce parasitic capacity other than an active layer in order to cope with a high speed modulation in an embedding hetero type semiconductor light element, in which the active layer is embedded in a semi-insulation semiconductor. <P>SOLUTION: An embedding layer 10 for semi-insulation semiconductor to be grown on both sides of a mesa stripe portion 18 including the active layer is formed from a first layer having the identical height to the mesa stripe portion 18, and a second layer, formed on the surface of the first layer along the mesa stripe portion 18, for growing it as far as both sides of a mask wider than the mesa stripe. The bottom 26 of a groove 28 where the second layer is not grown is formed to be flat and wide. Thus, the contact electrode 30 can be disposed in the bottom 26, and the narrowing of the bottom 26 reduces area and hence the parasitic capacitance of the electrode 30. An increase in the film thickness of the second embedding layer decreases a parasitic capacity between a pad electrode 34 and n-type substrate 2. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an optical semiconductor device (semiconductor optical element) having a buried mesa structure and a method for manufacturing the same, and more particularly to a semiconductor optical modulation device and an integrated semiconductor light emitting device in which the semiconductor optical modulation device is integrated.

A buried heterostructure (BH) type semiconductor optical device in which an active layer is embedded with a semi-insulating semiconductor is suitable for high-speed modulation operation because it can efficiently inject and extract carriers into the active region. For example, it is widely adopted in an electroabsorption (EA) type modulator integrated laser. FIG. 7 is a perspective view of a conventional element of a modulator integrated laser having a semi-insulating semiconductor BH structure. FIGS. 8 and 9 are vertical sectional views taken along lines aa and bb in FIG. Show. In order to cope with a high-speed modulation operation with a bit rate of 10 Gbit / sec or more, it is necessary to reduce the parasitic capacitance as much as possible. In general, the proportion of the capacitance (interelectrode capacitance) between the p-type electrode (anode electrode) and the n-type substrate in the parasitic capacitance other than the active layer of the semiconductor optical element having the BH structure is the largest. In order to reduce the interelectrode capacitance, conventionally, a method of increasing the film thickness _HSI0 of the semi-insulating semiconductor buried layer 10 sandwiched between the p-type electrode 12 and the n-type substrate 2, a semi-insulating semiconductor buried layer, 10 and a method of inserting a dielectric layer 14 between a pad electrode portion for wire bonding occupying a large area in the p-type electrode 12, a method of reducing the area of the pad electrode portion of the p-type electrode, and a mesa stripe This has been dealt with by a method of narrowing the electrode width L _EL0 of the portion 18.

Japanese Patent Laid-Open No. 7-226531

  In order to realize a higher-speed operation of 25 to 100 Gbit / second, which is a future prospect, further reduction of parasitic capacitance is essential, and it is necessary to further promote the above-described measures for reducing the capacitance.

However, the increase in the thickness of the dielectric layer 14 becomes severe in terms of process conditions in terms of ensuring uniformity within the wafer surface and occurrence of stepping of the p-type electrode. Therefore, the film thickness of the dielectric layer 14 is only about 5 μm. Regarding the p-type electrode area, the reduction of the pad electrode is limited by the wire bonding accuracy, and the reduction of the width of the mesa stripe portion 18 is a process of forming a contact through hole that is opened in the insulating film 16 on the mesa stripe portion 18. It is limited by the accuracy, and it is difficult to make them smaller than the current level. Under these circumstances, it is considered preferable to increase the thickness _HSI0 of the semi-insulating semiconductor buried layer 10 in order to further reduce the parasitic capacitance.

For example, a metal organic chemical vapor deposition (MOCVD) method is used to form the buried layer 10. The upper surface of the mesa stripe portion 18 is masked and selected on both sides of the unmasked mesa stripe portion 18. Indium, phosphorus (InP) or the like is grown as a crystal. At this time, if the height of the buried layer 10 is made higher than that of the mesa stripe portion 18, the step between the upper surface of the mesa stripe portion 18 and the upper surface of the buried layer 10 has (111) B such as InP constituting the buried layer 10. A slope with a surface is formed. The increase in the film thickness _HSI0 of the buried layer 10 is accompanied by a phenomenon that the region where the inclined surface is formed expands on both sides of the mesa stripe portion 18. In the pattern formation by photolithography on such a slope, the resolution is deteriorated due to the influence of light reflection or scattering during the exposure of the photoresist. This adverse effect increases the width L _TH0 of the through hole for contact of the p-type electrode 12 to the upper layer of the mesa stripe portion 18, and the flat upper surface of the buried layer 10 has the through hole edge outside the slope existing range. This can be avoided. For example, when the thickness of the buried layer 10 is 5 μm, the through hole width L _TH0 can be expanded to about 8 μm. As a result, the width L _EL0 of the contact electrode portion arranged along the mesa stripe portion 18 in the p-type electrode 12 increases, and the parasitic capacitance of this portion increases. That is, the buried layer 10 has a problem in that the parasitic capacitance is traded off between the pad electrode portion and the contact electrode portion of the p-type electrode 12 and the parasitic capacitance is not suitably reduced.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an optical semiconductor device in which the parasitic capacitance between the p-type electrode and the n-type substrate is suitably reduced, and a method for manufacturing the same. .

  An optical semiconductor device according to the present invention comprises a mesa stripe portion having an active layer formed on a substrate, and a semi-insulating semiconductor, and has both sides of the mesa stripe portion up to a height corresponding to the upper end of the mesa stripe portion. A buried layer that forms a buried mesa structure together with the mesa stripe portion; a contact electrode that extends along the mesa stripe portion on the upper surface of the buried mesa structure and is electrically connected to the mesa stripe portion; A base portion made of a semi-insulating semiconductor and formed higher than the buried layer in a region other than the region where the contact electrode is disposed, and disposed on the upper surface of the base portion, and the contact through the wiring A pad electrode for bonding connected to the electrode for use.

  According to a preferred aspect of the present invention, an electroabsorption modulator, a modulator section of an electroabsorption modulator integrated laser, a Mach-Zehnder modulator, and a modulator of a Mach-Zehnder modulator integrated laser are formed using the embedded mesa structure. 1 is an optical semiconductor device that constitutes either a direct current modulation type laser or a direct current modulation laser.

  In the optical semiconductor device according to the present invention, the semi-insulating semiconductor forming the buried layer and the semi-insulating semiconductor forming the plateau may contain iron or ruthenium.

  In the optical semiconductor device according to the present invention, the active layer can be composed of InGaAsP (indium gallium arsenic phosphorus) or InGaAlAs (indium gallium aluminum arsenic).

  The method for manufacturing an optical semiconductor device according to the present invention includes a step of forming the mesa stripe portion on the substrate, a top surface of the mesa stripe portion is covered with a mask, and a portion not covered with the mask is selectively A step of growing a buried layer and filling both sides of the mesa stripe portion with the buried layer to form the buried mesa structure; and a low-rise region including a region of the upper surface of the buried mesa structure where the contact electrode is formed Forming a plateau portion by selectively growing a layer made of the semi-insulating semiconductor in a portion not covered with the mask, and an insulator on the surface of the lowland region and the plateau portion Forming a protective film comprising: forming a through hole on the upper surface of the mesa stripe portion in the protective film; and forming the low hole after forming the through hole. Forming an electrode film made of a conductor on the surface of the region and the plateau, and patterning the electrode film using a photolithography technique to dispose the mesa through the through hole disposed only in the lowland region. Forming the contact electrode connected to the stripe portion, the pad electrode disposed on the upper surface of the plateau portion, and the wiring.

  According to the present invention, the thickness of the buried layer can be increased without increasing the width of the contact electrode disposed along the mesa stripe portion, and the parasitic capacitance of the contact electrode and the pad electrode is preferably reduced. It becomes possible to make it.

1 is a schematic perspective view of a semiconductor optical device having a BH structure according to a first embodiment. It is a typical vertical sectional view after the 1st embedding growth process of the semiconductor optical element concerning this invention. It is a typical vertical sectional view after mask formation with respect to the 2nd embedding growth process of the semiconductor optical element concerning this invention. It is a typical vertical sectional view after the 2nd embedding growth process of the semiconductor optical element concerning this invention. FIG. 2 is a schematic vertical sectional view of the semiconductor optical device according to the present invention taken along line aa in FIG. 1. FIG. 2 is a schematic vertical sectional view of the semiconductor optical device according to the present invention taken along line bb in FIG. 1. It is a perspective view of the conventional semiconductor optical element of a BH structure. FIG. 9 is a vertical sectional view of the conventional semiconductor optical device taken along line aa in FIG. 7. FIG. 8 is a vertical sectional view of the conventional semiconductor optical device taken along line bb in FIG. 7.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[First Embodiment]
The semiconductor optical device according to the present embodiment is a modulator integrated semiconductor laser device in which an EA modulator is monolithically integrated in front of a semiconductor laser. FIG. 1 is a schematic perspective view of this element. On the n-type InP substrate 2, a mesa stripe portion 18 having a BH structure is formed. The element has a laser forming region 20 in which a distributed feedback (DFB) laser is formed and a modulator forming region 22 in which an EA type modulator is formed. Both regions 20 and 22 are isolation grooves. 24 is electrically separated. Both regions 20 and 22 are provided with grooves 28 along the mesa stripe portion 18 and having a bottom surface 26 formed wide by two-stage formation of a buried layer 10 to be described later. In the modulator forming region 22, the p-type electrode 12 that is electrically connected to the contact layer located at the upper part of the mesa structure of the EA-type modulator is formed. The p-type electrode 12 includes a contact electrode 30, a pad electrode 34, and a wiring 36. The contact electrode 30 extends along the bottom surface 26 of the groove 28 and contacts the contact layer through a through hole opened in the insulating film 16 on the mesa stripe portion. The pad electrode 34 is an electrode for wire bonding, and is disposed in a region (a plateau portion) outside the groove 28. For example, in FIG. 1, the pad electrode 34 is circular. The pad electrode 34 is formed on the dielectric layer 14 stacked on the base portion of the buried layer 10. The wiring 36 in the p-type electrode 12 is a portion connecting the contact electrode 30 and the pad electrode 34. For example, the length of the contact electrode 30 (dimension in the extending direction of the mesa stripe portion 18), The width of the pad electrode 34 can be relatively small.

  Hereinafter, the manufacturing method of this element is demonstrated. Using the MOCVD method on the n-type InP substrate 2, an n-type InP buffer layer, an n-type InGaAsP light guide layer, an undoped InGaAsP active layer, a p-type InGaAsP light guide layer, a p-type InP spacer layer, and a p-type InGaAsP diffraction grating layer Then, a p-type InP cap layer is grown in this order (first stacked growth). As a result, a first laminated structure that functions as a DFB laser having a diffraction grating layer is formed.

  Next, an insulating film such as an oxide film or a nitride film is formed on the surface of the first stacked structure, and the insulating film is patterned to remove the insulating film from a region other than the laser formation region 20. Then, using the insulating film remaining in the laser forming region 20 as an etching mask, the first stacked structure is etched to the surface of the n-type InP buffer layer in the modulator forming region 22 by dry etching and wet etching. Next, an n-type InGaAsP light guide layer, an undoped InGaAsP active layer, a p-type InGaAsP light guide layer, and a p-type InP cap layer are formed in this order on the surface of the n-type InP buffer layer that appears by etching using the MOCVD method. Grows (second stacked growth). As a result, a second stacked structure that functions as an EA type modulator is formed in the modulator forming region 22 adjacent to the laser forming region 20.

  In the present embodiment, the first stacked structure for forming the DFB laser portion is formed before the second stacked structure for forming the EA type modulator portion. However, the order of forming these structures can be changed.

  Subsequently, the modulator forming region 22 in which the second laminated structure is formed is covered with an insulating film such as an oxide film or a nitride film, and this is used as an etching mask to start from the laser forming region 20 to the p-type InGaAs diffraction grating layer. The InP cap layer, which is a protective layer, is removed by etching. Thereafter, the diffraction grating layer is patterned by a photolithography technique to form a pattern in which a plurality of strip shapes whose longitudinal directions are oriented in a direction orthogonal to the optical axis are arranged in the optical axis direction. Thereby, a diffraction grating composed of diffraction grating layers periodically arranged in the optical axis direction is formed in the laser forming region 20.

  Thereafter, the p-type InP cap layer is removed from the modulator formation region 22, and a p-type InP clad layer, a p-type InGaAsP notch reduction layer, and a p-type InGaAs contact are formed on the modulator formation region 22 and the laser formation region 20 by MOCVD. A layer and an InP cap layer are grown in this order.

  Next, a stripe pattern mask 38 having a width of about 1 to 2.5 μm made of an insulating film is formed by photolithography. Using this mask 38, dry etching is performed to remove the laminated structure on both sides while leaving the laminated structure under the mask in a mesa shape. In this dry etching process, after reaching the n-type InP substrate 2, a depth of about 1.0 μm is further dug. Subsequently, in order to remove dry etching damage, the surface exposed by dry etching is etched by about 0.1 μm with a bromine-based solution. Thereby, a ridge stripe mesa structure is formed on the n-type InP substrate 2.

  Up to the formation of the mesa stripe portion 18 described above can be performed basically in the same process as the conventional one. A method for manufacturing the present element after the formation of the mesa stripe portion 18 will be described with reference to FIGS. 2 to 6 are schematic vertical cross-sectional views in the manufacturing process of the element, and show a vertical cross-section perpendicular to the extending direction of the mesa stripe portion 18.

  In a state where the mask 38 is disposed on the upper surface of the mesa stripe portion 18, burying growth is performed by semi-insulating InP doped with iron (Fe) or ruthenium (Ru) by MOCVD. As a result, the depressions on both sides of the mesa stripe portion 18 are buried, and the buried layer 40 is formed. The thickness of the buried layer 40 is the same as the height of the mesa stripe portion 18 or is raised to a level of 0.5 μm (first buried growth step). FIG. 2 is a vertical sectional view of a schematic element after the process. By the buried layer 40 formed in this step, the side surface of the mesa stripe portion 18 is sealed and a BH structure is completed.

  Next, the mask 38 is removed, and a new mask 42 having a stripe pattern made of an insulating film is formed on the mesa stripe portion 18. The mask 42 has a wider width than the mask 38. For example, the mask 42 is disposed around the mesa stripe portion 18 and has a wide width of 10 to 20 μm (FIG. 3).

  After the formation of the mask 42, a second buried growth step is performed in which the semi-insulating InP doped with Fe or Ru is again grown on the buried layer 40 by MOCVD (FIG. 4). The buried layer 44 grown in this step is basically grown to a position higher than the upper surface of the mesa stripe portion 18 in a region not covered with the mask 42. In this manner, the buried layer 10 shown in FIG. 1 of the present element is formed in two stages, the buried layer 40 and the buried layer 44. As will be described later, a pad electrode 34 is formed on the buried layer 44, and the capacitance generated between the pad electrode 34 and the n-type InP substrate 2 decreases as the thickness of the buried layer 10 under the pad electrode 34 increases. . The setting of the film thickness of the buried layer 44 has a relatively high degree of freedom, and the film thickness can be determined so that the parasitic capacitance of the pad electrode 34 is reduced to an allowable value.

  After the second burying growth step, the mask 42 of the mask insulating film is removed. The buried layer 44 does not grow in the portion covered with the mask 42, and the buried layer 10 in the portion has the thickness of the buried layer 40 formed in the first buried growth step. As a result, a low ground region having a low height is formed in the region including the mesa stripe portion 18, and a plateau portion having a height higher on both sides is formed. As a result, a groove along the mesa stripe portion 18 is formed. 28 is formed. The height of the bottom surface 26 of the groove 28, which is a lowland region, is basically the same as the top surface of the mesa stripe portion 18, and the bottom surface 26 corresponds to the width of the mask 42, as shown in FIG. Form.

  Subsequently, the manufacturing process after the buried growth will be described. After the second buried growth, the mask 42 is removed, and the entire surface is covered with an insulating film 16 such as an oxide film or a nitride film. Next, a through hole having a width of 3 to 5 μm centering on the mesa stripe portion 18 is opened on the insulating film by photolithography, and the p-type InP cap layer in the through hole is removed by etching, and a p-type InGaAs contact layer is formed. To expose. Subsequently, Ti / Pt / Au is sequentially laminated on the element surface (the buried layer 44 and the groove 28) as a conductive material by vacuum deposition to form an electrode film.

  The electrode film is patterned using a photolithography technique to form the p-type electrode 12. FIG. 5 and FIG. 6 are schematic vertical sectional views of the element on which the p-type electrode 12 is formed, respectively, showing the main part of the cross section along the lines aa and bb shown in FIG. 5 and 6 show the contact electrode 30 connected to the p-type InGaAs contact layer above the mesa stripe portion 18 through the through hole 46. In FIG. 5, the pad electrode 34 disposed on the upper surface of the buried layer 44 and the wiring 36 connecting the pad electrode 34 and the contact electrode 30 also appear.

The width of the bottom surface 26 can be arbitrarily designed by the two-stage formation of the buried layer 10 described above. Accordingly, the contact through hole 46 and the contact electrode 30 can be disposed in the bottom surface 26. That is, from the viewpoint of securing the edge resolution in each of the patterning for forming the through hole 46 in the insulating film 16 and the patterning for forming the p-type electrode 12 from the electrode film, the through hole 46 and the contact electrode are formed on the step slope of the buried layer 10. In order to avoid the arrangement of 30 edges, it is not necessary to increase the width L _TH1 of the through hole 46 or the width L _EL1 of the contact electrode 30 to the flat portion above the step. Thus, the width L _EL1 of the contact electrode 30 can be reduced together with the width L _TH1 of the contact through hole 46, and the parasitic capacitance caused by the contact electrode 30 can be reduced by reducing the area.

On the other hand, the pad electrode 34 is disposed on the upper surface of the base plate portion of the buried layer 10 where the film thickness _HSI1 can be increased independently of the bottom surface 26, and the pad electrode 34 is parasitic due to the increase in the film thickness _HSI1. Capacity is also reduced. In the present embodiment, since the dielectric layer 14 is laminated on the upper surface of the buried layer 44 and the pad electrode 34 is formed thereon, the distance from the n-type InP substrate 2 is further increased, and a single parasitic capacitance is formed. Reduction is being achieved.

  When the structure on the element surface side such as the formation of the p-type electrode 12 is formed, the back surface of the n-type InP substrate 2 is polished to a thickness of about 100 μm, and an n-type electrode (not shown) is formed on the back surface. Cleaving to expose the front and back of the device, and forming a low reflection film and a high reflection film on each surface by sputtering to form a chip, a modulator integrated semiconductor laser device is completed.

[Modification Example of First Embodiment (Part 1)]
In the above embodiment, the present invention is applied to the reduction of the parasitic capacitance of the p-type electrode 12 of the modulator section of the EA-type modulator, but this is applied to an element whose modulator section is a Mach-Zehnder type modulator. It can also be applied to the reduction of parasitic capacitance.

[Modification of First Embodiment (Part 2)]
In the above embodiment, the active layer material of the DFB laser part and the modulator part is InGaAsP, but the material of the active layer is not limited to this. For example, the present invention can be applied to an element in which the active layer is an InGaAlAs material. However, when Al is included in the active layer, there is a possibility that a current leakage component may be generated at the buried growth interface due to the influence of surface oxidation during the first buried growth in which the mesa stripe portion 18 is buried. Before the growth, surface treatment is performed with a halogen-based gas in an MOCVD furnace. After the first buried growth, the manufacturing process is the same as in the above-described embodiment.

[Modification of First Embodiment (Part 3)]
If narrowed width L _TH1 through hole 46 narrows the width L _EL1 of the contact electrode 30 accordingly, reduction of parasitic capacitance can be reduced by the area reduction. Accordingly, the through hole width _LTH1 can be further reduced by using an electron beam (EB) exposure method with high exposure accuracy. In that case, since the unevenness of the surface scanned with the beam may cause reflection and scattering of the beam and lower the exposure accuracy, it is required to ensure the flatness of the bottom surface 26 that forms the through hole 46.

  In this regard, when the buried layer 40 is simply grown by the MOCVD method as in the above-described embodiment, the buried layer 40 is slightly raised by the selective growth effect by the mask 38 in the vicinity of the mesa stripe portion 18, whereas the mesa A tendency to become lower in the vicinity may appear at a position away from the stripe portion 18.

Therefore, when the EB exposure method is employed, chemical mechanical polishing (CMP) processing may be performed in order to further improve the flatness of the bottom surface 26. In this case, the thickness of the first embedding growth is set in consideration of the thinning by the CMP process. For example, after the buried layer 40 is grown higher than the mesa stripe portion 18, it can be polished to the height of the mesa stripe portion 18 by CMP processing to obtain a uniformly flat surface within the wafer surface. Thereafter, the mask 38 of the mesa stripe portion 18 is removed, and a mask 42 having a width of 10 to 20 μm is formed again along the mesa stripe portion 18 to perform the second buried growth. Thereafter, the manufacturing process is basically the same as in the above embodiment. However, the through hole 46 of the mesa stripe part 18 is formed using the EB exposure apparatus as described above. Thus, the through-hole width _{L TH1} can be 1.5～3Myuemu, could further reduce the parasitic capacitance of the contact electrode 30.

[Second Embodiment]
The semiconductor optical device according to this embodiment is a direct current modulation semiconductor laser device. In the first embodiment described above, a DFB type laser part with a small wavelength variation by direct current operation is formed in the laser forming region 20, and the modulator part is adjacent to the modulator forming region 22 and the external modulator of the laser part. Was formed as. This configuration has an advantage that the temporal variation (chirping) of the laser wavelength is relatively easy, but is disadvantageous for cost reduction. In terms of this cost, a direct current modulation type semiconductor laser element that modulates the laser operating current with a direct signal is advantageous.

  In the laser element in which the external modulator is integrated, it is necessary to provide a difference in the laminated structure of the mesa stripe portion 18 between the modulator portion and the laser portion by the manufacturing process as described in the first embodiment. On the other hand, the direct current modulation type semiconductor laser device according to this embodiment does not have the structure of the mesa stripe portion 18 of the modulator portion, and basically the mesa stripe portion of the laser portion of the first embodiment. 18 has only the same configuration. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals for easy understanding.

  The manufacturing method of this element is basically the same as the manufacturing method of the laser part of the first embodiment, and an n-type InP buffer layer, an n-type InGaAsP light guide layer, An undoped InGaAsP active layer, a p-type InGaAsP light guide layer, a p-type InP spacer layer, a p-type InGaAsP diffraction grating layer, and a p-type InP cap layer are grown in this order. This is an active layer that functions as a DFB laser having a diffraction grating layer. Subsequently, a diffraction grating having a strip shape perpendicular to the optical axis is formed by photolithography, and then a p-type InP cladding layer, a p-type InGaAsP notch reduction layer, a p-type InGaAs contact layer, an InP are formed by MOCVD. Growing cap layer.

  The stacked structure thus formed is etched in the same manner as in the first embodiment to form the mesa stripe portion 18. Then, a buried layer 10 (embedded layers 40 and 44) made of semi-insulating InP doped with Fe or Ru is grown on both sides of the mesa stripe portion 18 by the same two-stage formation as in the first embodiment. Thus, a groove 28 having a wide and flat bottom surface 26 is formed on the surface of the buried layer 10 on the mesa stripe portion 18 of the laser portion, and a plateau portion is formed on both sides thereof.

The width L _{TH1 of the} contact through hole 46 to the p-type InGaAs contact layer of the mesa stripe portion 18 and the width L _EL1 of the contact electrode 30 are the minimum dimensions determined by the manufacturing process such as the processing means and alignment margin. Exists. The width of the bottom surface 26 is set so that at least the through holes 46 of the widths L _TH1 and L _EL1 corresponding to such minimum dimensions and the contact electrode 30 can be disposed in the bottom surface 26. Thereby, the contact electrode 30 can be formed in the bottom surface 26 with a narrow width _LEL1 , and the parasitic capacitance due to the contact electrode 30 can be reduced. In addition, the pad electrode 34 connected to the contact electrode 30 via the wiring 36 is disposed on a thick film plateau, thereby reducing the parasitic capacitance.

  Thus, in this element, the p-type electrode 12 to the mesa stripe part 18 of the laser part is formed with a structure in which the parasitic capacitance is reduced. When the structure on the element surface side such as the formation of the p-type electrode 12 is formed, the back surface of the n-type InP substrate 2 is polished to a thickness of about 100 μm, and the n-type electrode is formed on the back surface. Cleaving to expose the front and back of the device, and forming a low reflection film and a high reflection film on each surface by sputtering to form a chip, a modulator integrated semiconductor laser device is completed.

[Modification of Second Embodiment]
In the above embodiment, the active layer material of the laser part is InGaAsP, but the material of the active layer is not limited to this. For example, the present invention can be applied to an element in which the active layer is an InGaAlAs material. However, when Al is included in the active layer, a current leak component may be generated at the buried growth interface due to the effect of surface oxidation when the buried layer 40 in contact with the side surface of the mesa stripe portion 18 is grown. Before the surface treatment, a halogen-based gas is used in the MOCVD furnace.

  2 n-type InP substrate, 10 semi-insulating semiconductor buried layer, 12 p-type electrode, 14 dielectric layer, 16 insulating film, 18 mesa stripe portion, 20 laser forming region, 22 modulator forming region, 24 isolation groove, 26 bottom surface , 28 groove, 30 contact electrode, 34 pad electrode, 36 wiring, 38, 42 mask, 40, 44 buried layer, 46 through hole.

Claims (2)

A mesa stripe portion having an active layer formed on a substrate, and a semi-insulating semiconductor, filling both sides of the mesa stripe portion to a height corresponding to the upper end of the mesa stripe portion, and a buried mesa together with the mesa stripe portion A buried layer forming a structure, a contact electrode extending along the mesa stripe portion on the upper surface of the buried mesa structure and electrically connected to the mesa stripe portion, and a semi-insulating semiconductor, A plateau portion formed higher than the buried layer in a region other than the low-ground portion where the contact electrode is disposed; a bonding pad electrode disposed on the upper surface of the plateau portion and connected to the contact electrode; And a wiring connecting the contact electrode and the pad electrode, and the width of the low ground portion is 10 μm or more and 20 μm or less A manufacturing method for manufacturing an optical semiconductor device comprising:
Forming the mesa stripe portion on the substrate;
An upper surface of the mesa stripe portion is covered with a mask, and the buried layer is selectively grown on a portion not covered with the mask, and both sides of the mesa stripe portion are filled with the buried layer to form the buried mesa structure. Process,
A low ground region including a region for forming the contact electrode on the upper surface of the embedded mesa structure is covered with a mask, and a layer made of the semi-insulating semiconductor is selectively grown on a portion not covered with the mask. Forming the plateau,
Forming a protective film made of an insulator on the surface of the lowland region and the plateau part;
Forming a through hole on the upper surface of the mesa stripe portion in the protective film;
Forming an electrode film made of a conductor on the surface of the lowland region and the plateau after the through hole is formed;
The electrode film is patterned using a photolithographic technique, the contact electrode disposed only in the low-land region and connected to the mesa stripe portion through the through hole, and the top surface of the plateau portion. Forming a pad electrode and the wiring; and a method of manufacturing an optical semiconductor device. 2. The method of manufacturing an optical semiconductor device according to claim 1, wherein the optical semiconductor device uses the embedded mesa structure to provide an electroabsorption modulator, a modulator section of an electroabsorption modulator integrated laser, and a Mach-Zehnder modulator. method of manufacturing an optical semiconductor device, characterized in that is obtained by construction modulator of the Mach-Zehnder modulator integrated laser, and either a direct current modulation laser.

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