JP5310441B2 - Manufacturing method of semiconductor laser - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor laser that eliminates the need for wire bonding in packaging and having low ohmic resistance. <P>SOLUTION: A current block section is formed at both sides of an active layer on a first main surface of a mesa substrate. A second cladding layer and a contact layer are formed sequentially on the active layer and the current block section. An opening reaching the mesa substrate through the contact layer, second cladding layer, and current block section is formed by wet etching. A first ohmic electrode is formed on the contact layer. A first cladding layer is formed by performing rear surface polishing of the mesa substrate. A second ohmic electrode is formed on a second main surface of the first cladding layer. A side face electrode electrically connected to the second ohmic electrode is formed on an insulation film formed on an inner wall surface of the opening, and a first contact electrode electrically connected to the first ohmic electrode and a second contact electrode electrically connected to the side face electrode are formed on the insulation film formed on the contact layer. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor laser manufacturing method.

  For example, the semiconductor laser includes a lower cladding layer, an active layer, a p-type upper cladding layer, and a contact layer in this order on the first main surface side of the n-type substrate. In addition, ohmic electrodes are formed on the second main surface and the contact layer of the n-type substrate, respectively, and further, contact electrodes are formed on the ohmic electrodes (see, for example, Patent Document 1).

  When a semiconductor laser is mounted on a carrier, wire bonding is required for the contact electrode on one surface in the configuration in which the contact electrode is formed on both surfaces of the chip described above. When wire bonding is used, since a bonding electrode is required on the mounting substrate, the mounting area increases. Furthermore, there is a problem that the influence of the parasitic reactance due to the wire is large and high-speed modulation cannot be performed.

  On the other hand, there is a technique of providing ohmic electrodes as p-electrodes and n-electrodes of a semiconductor laser on the same surface side of a chip (for example, see Patent Document 2). By providing the p-electrode and the n-electrode on the same surface side, wire bonding is not necessary when the semiconductor laser is mounted on the coplanar line. For this reason, the mounting area can be reduced and the parasitic reactance due to the wire does not occur, so that the semiconductor laser can be modulated at high speed.

JP-A-9-246667 Japanese Patent Laid-Open No. 7-19312

  However, in the semiconductor laser in which the above-described conventional ohmic electrode is provided on the same side of the chip, the p-type ohmic electrode and the n-type ohmic electrode may be made of the same material.

  In this case, since a material showing optimum characteristics for both p-type and n-type cannot be selected, ohmic resistance becomes high.

  On the other hand, when the p-type and n-type ohmic electrodes are formed of different materials, the manufacturing process becomes complicated, for example, a photolithography process is required for each.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to provide a through electrode that electrically connects the ohmic electrode on the back side of the chip and the contact electrode on the front side. An object of the present invention is to provide a method of manufacturing a semiconductor laser that does not require wire bonding during mounting and has low ohmic resistance.

  In order to achieve the above-described object, the semiconductor laser manufacturing method of the present invention preferably includes the following steps.

  First, a first conductivity type substrate is prepared. Next, a precursor active layer and a precursor stripe cladding layer are sequentially formed on the first main surface of the substrate. Next, by patterning the precursor stripe cladding layer and the precursor active layer, respectively, the stripe cladding layer and the active layer are formed, and the substrate is mesa-etched to form the mesa substrate having the mesa structure portion on the first main surface side. To do. Next, current blocking portions are formed on both sides of the stripe cladding layer and the active layer on the first main surface of the substrate. Next, an upper second conductivity type cladding layer is formed on the stripe cladding layer and the current block portion, and a second cladding layer comprising the stripe cladding layer and the upper second conductivity type cladding layer is formed. Next, a contact layer is formed on the second cladding layer. Next, an opening reaching the mesa substrate through the contact layer, the second cladding layer, and the current block is formed by wet etching. Next, an insulating film is formed on the inner wall surface of the opening and on the contact layer. Next, a part of the insulating film is removed to expose a part of the contact layer, and a first ohmic electrode is formed on the exposed contact layer. Next, the first cladding layer is formed by polishing the back surface of the mesa substrate from the second main surface side. Next, a second ohmic electrode is formed on the second main surface of the first cladding layer. Next, a side electrode electrically connected to the second ohmic electrode is formed on the insulating film formed on the inner wall surface of the opening, and the first ohmic is formed on the insulating film formed on the contact layer. A first contact electrode electrically connected to the electrode and a second contact electrode electrically connected to the side electrode are formed.

  According to this semiconductor laser manufacturing method, since the opening is formed by wet etching, etching can be easily performed in a short time even with an etching depth of about 100 μm. Further, when the opening is formed by wet etching, the sectional shape of the opening becomes a tapered shape. That is, the opening on the chip surface (first main surface side) is the largest, and the opening gradually narrows toward the back surface of the substrate (second main surface side). For this reason, even if it is a depth of 100 micrometers, formation of the electrode by EB vapor deposition with respect to the side surface of opening becomes easy.

  According to the semiconductor laser manufactured by the above-described method, since the surface electrode used for mounting is formed on the same surface side of the wafer, the coplanar line can be mounted without using wire bonding. . As a result, no parasitic reactance due to the wire is generated, and high-speed modulation of the semiconductor laser can be expected.

  In addition, according to this method of manufacturing a semiconductor laser, the first ohmic electrode and the second ohmic electrode can be easily formed of appropriate materials, respectively, and thus ohmic resistance can be reduced.

It is process drawing (1) for demonstrating the manufacturing method of a semiconductor laser. It is process drawing (2) for demonstrating the manufacturing method of a semiconductor laser. It is process drawing (3) for demonstrating the manufacturing method of a semiconductor laser. It is process drawing (4) for demonstrating the manufacturing method of a semiconductor laser. It is process drawing (5) for demonstrating the manufacturing method of a semiconductor laser. It is a characteristic view of an etching rate. It is a figure for demonstrating the shape of the opening formed by wet etching.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(Semiconductor laser manufacturing method)
A method for manufacturing a semiconductor laser will be described with reference to FIGS. 1 (A) to (C), FIG. 2 (A) and (B), FIG. 3 (A) and (B), FIG. 4 (A) and (B), and FIG. 5 (A) and (B) FIG. 4 is a process diagram for explaining a method of manufacturing a semiconductor laser, and is a cut end view of a main part of a structure obtained in each process.

  First, for example, an n-InP substrate having a thickness of 350 μm is prepared as the substrate 25 of the first conductivity type (here, n-type).

  Next, the precursor active layer 35 and the precursor stripe cladding layer 55 are sequentially formed on the first main surface 25 a of the first conductivity type substrate 25. For example, the precursor active layer 35 is formed as an InGaAsP layer having a thickness of 0.15 to 0.20 μm. The precursor stripe clad layer 55 is made of, for example, p-InP having a thickness of 0.20 μm. The precursor active layer 35 and the precursor stripe clad layer 55 are formed by epitaxial growth using a conventionally known metal organic chemical vapor deposition (MOCVD) method (FIG. 1A).

  Next, the stripe cladding layer 52 and the active layer 30 are formed by patterning the precursor stripe cladding layer 55 and the precursor active layer 35, respectively. At this time, mesa etching of the first conductivity type substrate 25 is also performed to form the mesa substrate 26 having the mesa structure portion 24 on the base portion 23. In the following description, the process including patterning the precursor stripe cladding layer 55 and the precursor active layer 35 is referred to as mesa etching.

In this step, first, a silicon oxide film having a thickness of about 300 nm is formed on the surface of the precursor stripe cladding layer 55 by a conventionally known CVD method. Next, a resist pattern (not shown) is formed on the silicon oxide film using a conventionally known photolithography method. The width of the resist pattern is determined according to the design, but is set to 2.0 μm, for example. Next, the silicon oxide film 58 is formed by performing dry etching such as RIE (Reactive Ion Etching) using, for example, CF ₄ gas on the silicon oxide film using the resist pattern as a mask. Thereafter, the resist pattern used to form the silicon oxide film mask 58 is removed by any suitable method such as ashing, and then mesa etching is performed using the silicon oxide film mask 58.

This mesa etching is performed by RIE using Cl ₂ gas and wet etching using a mixed solution of HBr / HCl / H ₂ O ₂ / H ₂ O. In addition, the volume mixing ratio of the liquid mixture used for wet etching is, for example, HBr: HCl: H ₂ O ₂ : H ₂ O = 15: 75: 3: 200. The depth of mesa etching is controlled by this RIE. Further, the mesa structure portion 24, the active layer 30 and the stripe cladding layer 52 can be over-etched with respect to the silicon oxide film mask 58 by wet etching, and the width of the mesa structure portion 24, the active layer 30 and the stripe cladding layer 52 is increased. Is controlled (FIG. 1B).

  After the mesa etching, the current block portions 40 are formed on the mesa substrate 26 on the first main surface 26a side and on both sides of the stripe cladding layer 52 and the active layer 30. The current block unit 40 includes a p-InP current block layer 42 and an n-InP current block layer 44. The p-InP current blocking layer 42 and the n-InP current blocking layer 44 are formed by epitaxial growth by MOCVD (FIG. 1C).

  These current blocking layers (also referred to as current confinement layers) 42 and 44 reduce leakage current while strengthening lateral light confinement.

  Next, after the silicon oxide film mask 58 is removed by wet etching using hydrofluoric acid (HF), the upper second conductivity type (here, p-type) is formed on the stripe cladding layer 52 and the current block portion 40. .) The clad layer 54 is formed. The upper p-type cladding layer 54 is formed, for example, by epitaxially growing p-InP with a thickness of about 3.5 μm by MOCVD. The stripe cladding layer 52 and the upper p-type cladding layer 54 constitute a second cladding layer 50.

  Next, the contact layer 60 is formed on the second cladding layer 50. The contact layer 60 is formed by epitaxially growing p-InGaAs with a thickness of about 0.2 μm by MOCVD (FIG. 2A).

  Next, a silicon oxide film mask 59 used for forming an opening is formed on the upper surface 60 a of the contact layer 60.

In this step, first, a silicon oxide film having a thickness of about 300 nm is formed on the surface of the contact layer 60 by a conventionally known CVD method. Next, a resist pattern (not shown) is formed on the silicon oxide film using a conventionally known photolithography method. Next, dry etching such as RIE using CF ₄ gas is performed on the silicon oxide film using the resist pattern as a mask to form a silicon oxide film mask 59 to which the resist pattern is transferred. Thereafter, the resist pattern used to form the silicon oxide film mask 59 is removed by any suitable method such as ashing (FIG. 2B).

  Next, wet etching is performed using the silicon oxide film mask 59 to form an opening that reaches the mesa substrate through the contact layer, the second cladding layer, and the current block portion. The portions to be wet-etched include a mesa substrate 26 formed of n-InP, a p-InP current blocking layer 42, an n-InP current blocking layer 44, a second cladding layer 50 formed of p-InP, p A contact layer 60 made of InGaAs. For this reason, wet etching is performed in multiple stages.

The contact layer 60 is etched by, for example, wet etching using a mixed solution of sulfuric acid (H ₂ SO ₄ ), hydrogen peroxide water (H ₂ O ₂ ), and pure water (H ₂ O). The volume mixing ratio of the mixed solution used for wet etching is, for example, H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 3: 1: 1.

  Etching of the second cladding layer 50, the n-InP current blocking layer 44, the p-InP current blocking layer 42, and the mesa substrate 26 is performed using a hydrochloric acid-based etchant. Since this etching requires a deep etching of about 100 μm, it is preferable to perform the etching at a temperature higher than usual (FIG. 3A). The mesa substrate 26 is etched partway by etching with a depth of about 100 μm.

  An etching rate in wet etching using a hydrochloric acid-based etchant will be described with reference to FIG. FIG. 6 is a characteristic diagram of the etching rate. In FIG. 6, the horizontal axis represents the etching time (unit: minutes), and the vertical axis represents the etching depth (unit: μm). Here, the etching depth is a depth measured by using a laser microscope that does not include the silicon oxide film mask 59, that is, a depth from the upper surface 60a of the contact layer 60. FIG. 6 shows the measurement results when the etchant temperature is 25 ° C. (indicated by I in FIG. 6) and 4 ° C. (indicated by II in FIG. 6).

  For example, when a mixture of hydrochloric acid and pure water having a volume mixing ratio of 4: 1 is used as a hydrochloric acid-based etchant, the etching rate (I) is about 7 μm / min at 25 ° C. Therefore, 100 μm etching is completed in about 15 minutes. On the other hand, at 4 ° C., the etching rate (II) is about 1.5 μm / min. In this case, 60 minutes or more are required to complete the etching at a depth of 100 μm.

  Etching using this hydrochloric acid-based etchant has anisotropy as described later, and etching proceeds in the width direction of the laser. For this reason, the silicon oxide film mask 59 and the contact layer 60 may remain so as to partially cover the opening 95 (FIG. 3B).

Therefore, again, wet etching using a mixed solution of sulfuric acid (H ₂ SO ₄ ), hydrogen peroxide solution (H ₂ O ₂ ), and pure water (H ₂ O) is performed, and the contact layer 60 protruding to the opening is formed. Remove unnecessary parts.

  Next, after the silicon oxide film mask 59 is removed with hydrofluoric acid (HF), an insulating film 92 is formed on the bottom surface 95b and the inner wall surface 95a of the opening 95. The insulating film 92 is formed as a silicon oxide film by a CVD method, for example. At this time, an insulating film 64 is also formed on the contact layer 60 (FIG. 4A).

  Next, an ohmic electrode resist pattern (not shown) is formed on the insulating film 64. In the ohmic electrode resist pattern, a stripe-shaped opening having a width of 1.0 μm is formed in an upper region of the active layer 30. Next, wet etching using HF is performed using the resist pattern for ohmic electrodes as a mask to expose the region of the contact layer 60 above the active layer 30. Next, Au / AuZn / Au is deposited on the exposed contact layer 60. Thereafter, excess Au / AuZn / Au is removed by lift-off, and then heat treatment is performed to form an alloy to form the first ohmic electrode 70 (FIG. 4B).

  Next, the mesa substrate 26 is subjected to back surface polishing from the second main surface 26b side, and the first conductivity type first cladding layer 20 composed of the base portion 22 and the mesa structure portion 24 is formed. This back surface polishing is performed by, for example, mechanical polishing. The back surface polishing is performed until the thickness of the wafer reaches 100 μm, and is performed until the opening 95 penetrates. In addition, after forming the 1st clad layer 20, it can cleave in the surface which passes along the center of the opening 95, and can be isolate | separated into each chip | tip.

  Next, AuGeNi / Au is vapor-deposited on the second main surface 20b of the first cladding layer 20, and then heat-treated to be alloyed to form the second ohmic electrode 76 (FIG. 5A).

  Next, after forming a resist pattern by photolithography, Ti / Au is deposited by electron beam (EB) and so-called lift-off is performed to form the first contact electrode 80, the second contact electrode 86, and the side electrode 90. To do.

  The side electrode 90 is formed on the insulating film 92 formed on the inner wall surface 95 a of the opening 95 and is electrically connected to the second ohmic electrode 76. The first contact electrode 80 and the second contact electrode 86 are formed on the insulating film 64 formed on the contact layer 60. The first contact electrode 80 is electrically connected to the first ohmic electrode 70, and the second contact electrode 86 is electrically connected to the side electrode 92 (FIG. 5B).

  Through the process described above, a semiconductor laser having an electrode for applying a voltage on the same surface side is manufactured.

According to this semiconductor laser manufacturing method, the opening is formed by wet etching using a hydrochloric acid-based etchant. For this reason, even if it is an etching about 100 micrometers deep, it can etch easily in a short time. When using an etchant having a volume mixing ratio of hydrochloric acid and pure water of 4: 1, an etching rate of 7 μm / min is obtained at 25 ° C., so that etching of 100 μm can be performed in about 15 minutes. For example, when InP is dry-etched with an ICP-RIE layer using ordinary Cl ₂ , the etching rate takes about 1.5 μm / min, and processing takes time, and processing is performed accurately with a high aspect ratio of 100 μm in depth. It is difficult.

  Further, the cross section of the opening 95 formed by wet etching has a tapered shape. That is, the opening on the chip surface (first main surface side) is the widest, and gradually becomes narrower toward the substrate back surface (second main surface side). For this reason, even if it is a depth of 100 micrometers, formation of the electrode by EB vapor deposition with respect to the side surface of opening becomes easy.

  Note that wet etching using a hydrochloric acid-based etchant has anisotropy, and the cross-sectional shape differs depending on the crystal orientation. The shape of the opening will be described with reference to FIG.

  FIG. 7 is a schematic diagram for explaining the shape of the opening formed by wet etching using a hydrochloric acid-based etchant. FIG. 7A is a plan view of a mask pattern (silicon oxide film mask) 59 formed of a silicon oxide film. FIG. 7B is a plan view of the opening 95 formed by wet etching. FIG. 7C is a diagram showing a cut end surface cut along a direction corresponding to the line AA in FIG. FIG. 7D is a diagram showing a cut end surface cut along a direction corresponding to the line BB in FIG. 7B. 7C and 7D, the size of the opening of the mask pattern is ignored. In FIG. 7, illustration of electrodes and the like is omitted, but the AA line in FIG. 5B corresponds to the resonance direction of the semiconductor laser. 7B corresponds to the direction orthogonal to the resonance direction of the semiconductor laser.

  In the cross section shown in FIG. 7C, the taper angle θ of the opening is 33 °. Here, the taper angle θ refers to an angle between the center line of the opening and the inner wall surface 95b of the opening 95 from the apex 95c located at the bottom of the opening 95 toward the first main surface 96a. On the other hand, in the cross section shown in FIG. 7D, the taper angle θ of the opening is 57 °. Due to this etching anisotropy, when the opening is formed at a depth of 100 μm, the size of the opening on the chip surface is about 300 μm × 130 μm, and the occupied area with respect to a general chip size (300 μm × 250 μm) of a semiconductor laser Is big.

  Therefore, if a plurality of laser chips are formed on one wafer and an opening is formed in the middle of adjacent laser chips, the area to be etched per laser chip can be reduced. In this case, the cleavage is performed on a plane passing through the center of the opening. As shown in FIG. 5B, the ohmic electrode 76 formed on the back surface side and the contact electrode 86 on the front surface side are connected by the side electrode 90. Therefore, there is no problem in electrical characteristics.

  Although the method for forming the first contact electrode, the second contact electrode, and the side electrode by vapor deposition has been described here, it may be formed by a plating method. The inside of the opening 95 is filled with an electrode material such as copper (Cu) by plating. In this case, since the inside of the opening is filled with a metal material having a higher thermal conductivity than air, heat dissipation is improved and temperature characteristics are improved.

  According to the semiconductor laser manufactured by the above-described method, since the contact electrode used for mounting is formed on the same surface side of the wafer, the coplanar line can be mounted without using wire bonding. . As a result, no parasitic reactance due to the wire is generated, and high-speed modulation of the semiconductor laser can be expected.

  According to the embodiment of the semiconductor laser, the first ohmic electrode 70 is made of AuGeNi / Au, and the second ohmic electrode 82 is made of AuZn / Au. As described above, since the first ohmic electrode and the second ohmic electrode can be easily formed of appropriate materials, ohmic resistance can be reduced.

20 First cladding layer (lower cladding layer)
22, 23 Base portion 24 Mesa structure portion 25 Substrate 26 Mesa substrate 30 Active layer 35 Precursor active layer 40 Current block portion 42 p-InP current block layer 44 n-InP current block layer 50 Second clad layer (upper clad layer)
52 stripe clad layer 54 upper second conductivity type (p-type) clad layer 55 precursor stripe clad layer 58, 59 silicon oxide film mask 60 contact layer 64, 92 insulating film 70 first ohmic electrode 76 second ohmic electrode 80 first contact Electrode 86 Second contact electrode 90 Side electrode

Claims (5)

Preparing a first conductivity type substrate;
Sequentially forming a precursor active layer and a precursor stripe cladding layer on the first main surface of the substrate;
The precursor stripe clad layer and the precursor active layer are patterned to form a stripe clad layer and an active layer, respectively, and the substrate is mesa etched to have a mesa structure on the first main surface side of the substrate. Forming a mesa substrate;
Forming a current blocking portion on both sides of the stripe cladding layer and the active layer on the first main surface of the substrate;
Forming an upper second conductivity type clad layer on the stripe clad layer and the current block, and forming a second clad layer comprising the stripe clad layer and the upper second conductivity type clad layer;
Forming a contact layer on the second cladding layer;
Forming an opening reaching the mesa substrate through the contact layer, the second clad layer, and the current block portion by wet etching;
Forming an insulating film on the inner wall surface of the opening and on the contact layer;
Removing a portion of the insulating film to expose a partial region of the contact layer, and forming a first ohmic electrode on the exposed contact layer;
Forming a first cladding layer by polishing the back surface of the mesa substrate from the second main surface side;
Forming a second ohmic electrode on the second main surface of the first cladding layer;
A side electrode electrically connected to the second ohmic electrode is formed on the insulating film formed on the inner wall surface of the opening, and the first electrode is formed on the insulating film formed on the contact layer. Forming a first contact electrode electrically connected to the ohmic electrode and a second contact electrode electrically connected to the side electrode; 2. The method of manufacturing a semiconductor laser according to claim 1, wherein the first ohmic electrode and the second ohmic electrode are formed of different materials. 3. The method of manufacturing a semiconductor laser according to claim 1, wherein the first contact electrode, the second contact electrode, and the side electrode are formed by an electron beam evaporation method. 3. The method of manufacturing a semiconductor laser according to claim 1, wherein the first contact electrode, the second contact electrode, and the side electrode are formed by a plating method. 5. The method of manufacturing a semiconductor laser according to claim 1, wherein, after the step of forming the first cladding layer, cleaving is performed on a plane passing through a center of the opening.

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