JP2009117616A - Method for manufacturing semiconductor optical element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor optical element capable of suppressing chipping and cracking that occur in a chip during scribing. <P>SOLUTION: A semiconductor optical element 50b is provided with group III-V compound semiconductor layer 26a, along the edge of the backside of an InP support base 10a. It is preferable that an insulating layer 30 be provided on the InP layer 24. An electrode 32 is provided on a semiconductor mesa 22 and connected to the semiconductor mesa 22 via an opening of the insulating layer 30. To the electrode 32, an electrode pad 32a, located on the insulating layer 30, is connected. The electrode pad 32a is distant from a cleavage area. To the electrode pad 32a, a wire is bonded. The electrode area of the backside of the InP support base 10a is provided with an electrode 34. In the semiconductor optical element 50, a current is injected into an active layer 12a of the semiconductor mesa 22. A section of the semiconductor mesa appears from the backside of the substrate, on the cleavage surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for fabricating a semiconductor optical device.

Patent Document 1 describes a method of manufacturing a semiconductor laser element. In this manufacturing method, an InP buried layer is formed around the mesa structure by a low pressure metal organic chemical vapor deposition method of about 20 to 100 torr. Hydrogen chloride (HCl) is added to the source gas in the range of, for example, 0.1 to 1.0 in terms of the group III source gas ratio. An n-electrode is formed on the back surface of the InP substrate, and a p-electrode is formed on the top surface of the semiconductor mesa.
JP 08-78793 A

  In the production of a semiconductor optical device, an electrode is formed by a metallization process after the growth of a semiconductor crystal on a wafer is completed. Thereafter, scribing is performed for manufacturing a semiconductor chip or a laser bar. However, when the outermost crystal is an InP crystal, the wafer may be cleaved at a position different from the scribe position during scribing. Also, chips may be chipped or cracked during cleavage. These cause appearance defects and characteristic defects. In the production of a semiconductor optical device, since scribing and cleavage are used, it is desired to reduce chipping and cracking that occur during scribing.

  The present invention has been made in view of the above-described matters, and an object of the present invention is to provide a method for producing a semiconductor optical device capable of reducing chipping or cracking that occurs during scribing.

  One aspect of the present invention is a method for fabricating a semiconductor optical device. In this method, (a) a Ga substrate is formed on a scribe area on the back surface of an epitaxial substrate having a supporting base made of a III-V group compound semiconductor and a III-V group compound semiconductor structure provided on the main surface of the supporting base. Forming a group III-V compound semiconductor layer containing In, As, and As; and (b) first on the back surface of the epitaxial substrate so that the surface of the group III-V compound semiconductor layer is exposed. And (c) scribing the III-V group compound semiconductor layer on the scribe area, and cleaving to produce a semiconductor piece for a semiconductor optical device, The III-V compound semiconductor structure includes a plurality of epitaxial layers for the semiconductor optical device.

  According to this method, since the surface of the III-V group compound semiconductor layer containing Ga, In, and As is scribed, compared with the case where the surface of the InP layer is scribed, the surface of the III-V group compound semiconductor layer is formed. A groove suitable for cleavage is formed. Therefore, when the InP layer and the InP substrate are cleaved, the InP layer and the InP substrate are cleaved with high accuracy along the scribe line. Therefore, generation | occurrence | production of the crack and a chip | tip in a cleavage surface is reduced. Moreover, since the III-V compound semiconductor layer is provided on the back surface of the substrate, the addition of the III-V compound semiconductor layer has little influence on the device characteristics.

In the method according to the present invention, the group III-V compound semiconductor structure includes a semiconductor mesa extending in a first direction and having an active layer, and the scribe area extends in a second direction intersecting the first direction. The III-V compound semiconductor layer is provided on the first portion of the scribe area, and the semiconductor piece is a cleavage plane extending in the second direction. A cross section of the semiconductor mesa appears on the cleavage surface of the semiconductor piece. According to this method, since the cross section of the semiconductor mesa appears on the cleavage plane, the end surface of the active layer is formed by the cleavage plane. The occurrence of cracks and chips on the end face of the active layer can be reduced.
In the method according to the present invention, the scribe area has a second portion extending in a third direction intersecting the second direction, and the III-V group compound semiconductor layer includes the scribe area. Provided on the second portion of the area, the scribe area extends in a third direction intersecting the second direction, and the semiconductor piece for the semiconductor optical device comprises the third piece The cleaved surface extends in the direction of.

  The method according to the present invention may further include a step of forming the epitaxial substrate by forming the III-V compound semiconductor structure on the substrate and then reducing the thickness of the substrate. According to this method, since the group III-V compound semiconductor layer is formed after grinding the back surface of the substrate, the semiconductor optical device can be manufactured to a desired thickness.

  In the method according to the present invention, the group III-V compound semiconductor structure includes a semiconductor mesa extending in a first direction and having an active layer, and a current block region embedding the semiconductor mesa. A doped InP layer is included, and iron-doped InP in the current blocking region appears on the cleavage plane. According to this method, even in a semiconductor optical device in which the current block region includes an iron-doped InP region, it is possible to avoid scribing the iron-doped InP region.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, there is provided a method for manufacturing a semiconductor optical device capable of reducing chipping and cracking that occur during scribing.

The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a semiconductor optical device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.
(First embodiment)

  1 to 3 are drawings schematically showing a method of manufacturing a semiconductor optical device according to an embodiment. The semiconductor optical device includes, for example, a semiconductor laser. As shown in FIG. 1A, a plurality of semiconductor films are formed over the InP substrate 10. These semiconductor films are made of a III-V compound semiconductor. For example, a first conductivity type cladding layer 11, an active layer 12, a second conductivity type cladding layer 14, and a second conductivity type contact layer 16 are formed in this order on a first conductivity type InP substrate 10. The stacked body 19 includes a first conductivity type cladding layer 11, an active layer 12, a second conductivity type cladding layer 14, and a second conductivity type contact layer 16. The InP substrate 10 may include an InP buffer layer on the surface thereof. The active layer 12 can have a multiple quantum well structure. In this embodiment, the thickness of the contact layer 16 is, for example, 0.2 to 0.5 μm.

An example of the laminated body 19 has the following structure.
Clad layer 11: n-type InP, 0.5 μm
Active layer 12: For example, GaInAsP, AlGaInAs, 0.3 μm
Clad layer 14: p-type InP, 2.0 μm
Contact layer 16: p-type GaInAs, 0.2 μm

Next, as illustrated in FIG. 1B, an insulating film 20 is deposited over the stacked body 19. The insulating film 20 can be made of, for example, SiO ₂ , SiN or the like. In one embodiment, the thickness of the insulating film 20 is, for example, 0.3 μm. Using photolithography and etching, a pattern is formed on the insulating film 20 as shown in FIG. By this processing, a mask 20a is formed on the stacked body 19. The pattern shape of the mask 20a is, for example, a stripe shape, and the width of the stripe is, for example, 0.8 to 1.5 μm.

Next, as shown in FIG. 1D, a semiconductor mesa 22 is formed on the InP substrate 10. In order to form the semiconductor mesa 22, the stacked body 19 is etched using the mask 20 a and a part of the cladding layer 11 of the first conductivity type is etched. The semiconductor mesa 22 can be formed by dry etching (RIE), and the etchant includes, for example, CH ₄ gas and H ₂ gas. It is preferable to perform wet etching of, for example, about 0.1 μm after dry etching. The semiconductor mesa 22 can include an active layer 12a, a cladding layer 14a, and a contact layer 16a, and these layers are stacked in this order. The semiconductor mesa 22 has an optical waveguide structure. The semiconductor mesa 22 is formed in a stripe shape, for example.

  Next, as shown in FIG. 2A, a buried region is formed on the InP substrate 10 using a mask 20a so as to bury the semiconductor mesa 22. The buried region can be composed of, for example, an InP region 24. For example, the InP region 24 is Fe-doped. The InP region 24 is formed by, for example, metal organic chemical vapor deposition (OMVPE). The InP region 24 is preferably formed so that its surface is substantially at the same position as the top surface of the semiconductor mesa 22. Through these steps, a III-V compound semiconductor structure was formed on the InP substrate.

After forming the InP region 24, the mask 20a is removed. This removal is performed by, for example, an HF etchant. Next, as shown in FIG. 2B, an insulating film 30 is formed on the semiconductor mesa 22 and the InP layer 24. The insulating film 30 can be made of, for example, SiO ₂ , SiN or the like.

  If necessary, the back surface 10b of the InP substrate 10 is ground. By this grinding, the thickness of the InP substrate 10 is reduced, and the epitaxial substrate E1 including the III-V group compound semiconductor structure and the InP support base 10a is manufactured. The epitaxial substrate E1 includes a front surface 10c and a back surface 10d of the InP support base 10a. The thickness D1 of the InP substrate 10 is, for example, 300 μm, and the thickness D2 of the InP support base 10a is, for example, 100 μm.

  Subsequently, as shown in FIG. 2D, the III-V group compound semiconductor layer 26 is formed on the back surface 10b of the InP support base 10a. The III-V compound semiconductor layer 26 contains Ga, In, and As as constituent elements. The III-V compound semiconductor layer 26 can be made of, for example, GaInAs, GaInAsP, or the like. The III-V compound semiconductor layer 26 is preferably made of a single crystal lattice-matched with InP. The thickness of the III-V compound semiconductor layer 26 is preferably 0.1 μm to 0.2 μm. The III-V compound semiconductor layer 26 is preferably undoped. This is because undoped can suppress the diffusion of impurities into the substrate or the active layer, and the increase in lattice mismatch between the III-V compound semiconductor layer and the InP substrate. Even when the III-V compound semiconductor layer 26 is doped with impurities, it is preferable to dope impurities having the same conductivity type as that of the InP substrate. This is because even when the impurities diffuse into the InP substrate or the like, the impurities can compensate each other and increase in electrical resistance can be suppressed. The III-V compound semiconductor layer 26 is not limited to being composed of a single-layer semiconductor film, and may have a multilayer structure.

  After the III-V group compound semiconductor layer 26 is formed, a mask 28 is formed on the III-V group compound semiconductor layer 26 as shown in FIG. The mask 28 is made of, for example, a resist. As shown in FIG. 3B, the III-V compound semiconductor layer 26 is patterned by etching using a mask 28 to form a III-V compound semiconductor layer 26a for scribing. The III-V compound semiconductor layer 26 is etched by, for example, a phosphoric acid etchant. Thereafter, the mask 28 is removed. The III-V compound semiconductor layer 26a is provided on the scribe area 10e on the back surface 10d of the InP support base 10a, and is not formed on the electrode area 10f different from the scribe area 10e. Note that pattern formation may not be performed on the III-V compound semiconductor layer 26a. In this case, an n-type dopant is added to the III-V compound semiconductor layer 26.

FIG. 4 is a drawing showing the back surface 10d of the epitaxial substrate E1. The III-V compound semiconductor layer 26a includes a region 26b extending in the x-axis direction of the coordinate system S and a region 26c extending in the y-axis direction of the coordinate system S. The III-V compound semiconductor layer 26a is provided on the scribe area 10e on the back surface 10d. The electrode area 10f on the back surface 10d is surrounded by the region 26b and the region 26c. Region 26c is provided along the reference plane S _X which is located between the semiconductor mesa 22, region 26b is provided along the reference plane S _Y extending in a direction perpendicular to the semiconductor mesa 22.

  As shown in FIG. 3C, an opening 30 a is formed in the insulating film 30. The opening 30a is formed by, for example, a photolithography method. The opening 30 a is provided, for example, on the stripe-shaped semiconductor mesa 22 and extends along the semiconductor mesa 22. The width of the opening 30 a is wider than the width of the upper surface of the semiconductor mesa 22. The front surface of the epitaxial substrate E1 has a cleavage area, and this cleavage area corresponds to the scribe area 10e on the back surface 10 of the epitaxial substrate E1. The insulating film 30b covers the cleavage area.

  Next, as shown in FIG. 3D, the electrode 32 is formed on the semiconductor mesa 22 by lift-off, and the electrode 34 is formed on the back surface 10d of the InP support base 10a by lift-off. The electrode 32 is formed on each semiconductor mesa 22 and is electrically connected to the contact layer 16a. The electrode 32 is formed in the opening 30 a of the insulating layer 30 b and extends along the extending direction of the striped semiconductor mesa 22. The electrode 34 is formed on the electrode area 10f of the back surface 10d of the epitaxial substrate E1. The electrode 34 is surrounded by the III-V compound semiconductor layer 26a. The electrode 34 is preferably separated from the III-V compound semiconductor layer 26a. This is because it is possible to prevent the electrodes from being damaged by a scribing device (tool) during scribing.

  FIG. 5 is a drawing showing the back surface 10d of the epitaxial substrate E1. As shown in FIG. 5, the III-V compound semiconductor layer 26a is scribed. For example, the surface 26 of the III-V compound semiconductor layer 26a is scribed in the x-axis direction. The scribing is performed using a scribing device 36 such as a diamond pen, for example. As a result, a scribe groove 26g is formed on the III-V compound semiconductor layer 26a.

  The scribe groove 26g can be formed in a direction intersecting with the extending direction of the semiconductor mesa 22 (for example, the <100> direction of the III-V compound semiconductor layer 26a). The scribe groove 26g is preferably formed at the edge of the InP support base 10a. Since the semiconductor optical device is not formed in the edge region of the InP support base 10a, the device characteristics are not affected by forming the scribe groove 26g in the semiconductor optical device 50. Further, when the scribe groove 26g is formed in the edge region of the InP support base 10a along the direction intersecting with the extending direction of the semiconductor mesa 22 formed in a stripe shape, the light emitting surface (for example, mirror surface) of the semiconductor optical device 50 is formed. ), No scribe groove 26g remains, so that the characteristics of the semiconductor optical device are improved.

Next, FIG. 6 is a drawing showing a semiconductor piece 50a such as a laser bar formed by cleavage. As shown in FIG. 6, starting from the scribe groove 26a formed along the reference plane _{S Y,} InP layer 24, and cleaving the InP supporting substrate 10a. For example, the cleavage is preferably performed by pressing the blade against the scribe line. By cleaving, the semiconductor piece 50a is formed from the InP support base 10a. By producing the semiconductor piece 50a, a light emitting surface for the semiconductor optical device 50 can be formed. Next, after cleaving along the direction (x-axis direction) intersecting the extending direction of the semiconductor mesa 22 formed in a stripe shape, scribing is performed in the extending direction (y-axis direction) and cleavage is performed. Preferably it is done. In the semiconductor element 50a, the semiconductor mesa 22 extends along a reference plane _{S M.}

  Through the above steps, the semiconductor optical device 50b shown in FIG. 7 was manufactured. FIG. 7 is a perspective view schematically showing a semiconductor optical device manufactured by the method of manufacturing a semiconductor optical device according to the embodiment. Examples of the semiconductor optical device 50b shown in FIG. 7 include a semiconductor laser, an optical amplifier, an optical modulator, and an integrated device in which two or more of these devices are combined.

  As shown in FIG. 7, the semiconductor optical device 50b is provided on the InP support base 10a, the semiconductor mesa 22 formed on the InP support base 10a, the InP layer 24 in which the semiconductor mesa 22 is embedded, and the InP layer 24. Insulating film 30b. A III-V compound semiconductor layer 26a is provided along the edge of the back surface 10d of the InP support base 10a. An insulating layer 30b is preferably provided on the InP layer 24. An electrode 32 is provided on the semiconductor mesa 22 and connected to the semiconductor mesa 22 through an opening of the insulating layer 30b. An electrode pad 32a located on the insulating layer 30b is connected to the electrode 32. The electrode pad 32a is away from the cleavage area. An electrode 34 is provided in the electrode area 10f on the back surface 10d of the InP support base 10a. In the semiconductor optical device 50b, current is injected into the active layer 12a of the semiconductor mesa 22.

  The III-V compound semiconductor structure includes a semiconductor mesa 22 having an active layer 12a extending in the x-axis direction, and the scribe area 10e has a portion extending in the y-axis direction intersecting the x-axis direction. The semiconductor pieces 50a and 50b for the semiconductor optical element have a cleavage plane extending in the y-axis direction, and a cross section of the semiconductor mesa appears on the cleavage plane. Since the cross section of the semiconductor mesa 22 appears on the cleavage plane, the end face of the active layer 12a is formed of the above cleavage plane. It is possible to reduce the occurrence of cracks and chips on the end face of the active layer 12a.

  The scribe area 10e has a portion extending in the x-axis direction intersecting the y-axis direction. The scribe area 10e extends in the x-axis direction, and the semiconductor piece 50b has a cleavage plane extending in the x-axis direction. An InP layer 24 for embedding appears on the cleavage plane.

  As described above, in the method for manufacturing a semiconductor optical device according to the present embodiment, the III-V compound semiconductor layer 26a containing Ga, In, and As is formed on the back surface of the substrate, and the III-V compound semiconductor layer 26a. Therefore, a sharp groove is formed on the surface of the III-V compound semiconductor layer 26a as compared with the case where the surface of the InP layer is scribed. Therefore, when cleaving the semiconductor mesa 22, InP layer 24 and InP support base 10a, the semiconductor mesa 22, InP layer 24 and InP support base 10a are cleaved along a desired scribe area. Therefore, the generation of cracks and chips on the cleavage plane is reduced, and therefore the characteristics of the semiconductor optical device 50b are not impaired by the generation of cracks and chips.

  According to the knowledge of the inventors, since the Fe-doped InP surface is easily crushed, the surface of the Fe-doped InP may be scribed and cracks or chips may be generated on the cleavage plane. However, in the method for manufacturing a semiconductor optical device of the present embodiment, the occurrence of cracks and chips on the cleavage plane of the Fe-doped InP layer 24 is reduced.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a drawing schematically showing a method for manufacturing a semiconductor optical device according to an embodiment. FIG. 2 is a drawing schematically showing a method for manufacturing a semiconductor optical device according to the embodiment. FIG. 3 is a drawing schematically showing a method for manufacturing a semiconductor optical device according to the embodiment. FIG. 4 is a view showing the back surface of the epitaxial substrate. FIG. 5 is a drawing showing the back surface of the epitaxial substrate. FIG. 6 is a diagram showing a semiconductor piece such as a laser bar formed by cleavage. FIG. 7 is a perspective view schematically showing a semiconductor optical device manufactured by the method of manufacturing a semiconductor optical device according to the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... InP board | substrate, 11 ... 1st conductivity type clad layer, 12 ... Active layer, 14 ... 2nd conductivity type clad layer, 16 ... 2nd conductivity type contact layer, 12a ... Active layer, 14a ... Cladding layer, 16a ... contact layer, 19 ... laminated body, 20 ... insulating film, 20a ... mask, 22 ... semiconductor mesa, 24 ... InP region, 10b ... back of InP substrate, 10c ... surface of InP support base, 10d ... of InP support base Back surface, 10e ... scribe area, 10f ... electrode area, 26 ... III-V group compound semiconductor layer, 26a ... III-V group compound semiconductor layer, 26b, 26c ... region of III-V group compound semiconductor layer, 26g ... scribe groove , 28 ... mask, 30a ... opening, 30, 30B ... insulating film, 32a ... electrode pad, 32, 34 ... electrode, 50a ... semiconductor piece, 50b ... semiconductor optical _device, S X, _{S Y} , S _M ... reference plane, E1 ... epitaxial substrate

Claims (5)

A method for producing a semiconductor optical device, comprising:
Ga, In, and As are included on the scribe area on the back surface of the epitaxial substrate having a support base made of a III-V group compound semiconductor and a III-V group compound semiconductor structure provided on the main surface of the support base. Forming a III-V compound semiconductor layer;
Forming a first electrode on the back surface of the epitaxial substrate such that a surface of the III-V compound semiconductor layer is exposed;
Scribing the III-V group compound semiconductor layer on the scribe area, and cleaving to produce a semiconductor piece for a semiconductor optical device,
The III-V compound semiconductor structure includes a plurality of epitaxial layers for the semiconductor optical device. The III-V compound semiconductor structure includes a semiconductor mesa extending in a first direction and having an active layer;
The scribe area has a first portion extending in a second direction intersecting the first direction;
The III-V compound semiconductor layer is provided on the first portion of the scribe area,
The semiconductor piece has a cleavage plane extending in the second direction;
The method according to claim 1, wherein a cross section of the semiconductor mesa appears on the cleaved surface of the semiconductor piece. The scribe area has a second portion extending in a third direction intersecting the second direction;
The III-V compound semiconductor layer is provided on the second portion of the scribe area,
The scribe area extends in a third direction intersecting the second direction;
3. The method of claim 2, wherein the semiconductor piece for the semiconductor optical device has a cleaved surface extending in the third direction.   4. The method according to claim 1, further comprising: forming the epitaxial substrate after forming the group III-V compound semiconductor structure on the substrate, reducing the thickness of the substrate. 5. The method as described in any one. The III-V compound semiconductor structure includes a semiconductor mesa extending in a first direction and having an active layer, and a current blocking region that embeds the semiconductor mesa.
The current blocking region includes an iron-doped InP layer;
The method of claim 1, wherein iron-doped InP in the current blocking region appears on a cleavage plane.

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