DE69422265D1 - Verfahren zur Herstellung einer strahlungsgeschützten Silizium-auf-Isolator Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer strahlungsgeschützten Silizium-auf-Isolator Halbleiteranordnung

Info

Publication number
DE69422265D1
DE69422265D1 DE69422265T DE69422265T DE69422265D1 DE 69422265 D1 DE69422265 D1 DE 69422265D1 DE 69422265 T DE69422265 T DE 69422265T DE 69422265 T DE69422265 T DE 69422265T DE 69422265 D1 DE69422265 D1 DE 69422265D1
Authority
DE
Germany
Prior art keywords
radiation
producing
semiconductor device
insulator semiconductor
protected silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69422265T
Other languages
English (en)
Other versions
DE69422265T2 (de
Inventor
Frederick T Brady
Nadim F Haddad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Information and Electronic Systems Integration Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69422265D1 publication Critical patent/DE69422265D1/de
Application granted granted Critical
Publication of DE69422265T2 publication Critical patent/DE69422265T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE69422265T 1993-10-28 1994-10-14 Verfahren zur Herstellung einer strahlungsgeschützten Silizium-auf-Isolator Halbleiteranordnung Expired - Lifetime DE69422265T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/142,030 US5360752A (en) 1993-10-28 1993-10-28 Method to radiation harden the buried oxide in silicon-on-insulator structures

Publications (2)

Publication Number Publication Date
DE69422265D1 true DE69422265D1 (de) 2000-01-27
DE69422265T2 DE69422265T2 (de) 2000-07-13

Family

ID=22498281

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69422265T Expired - Lifetime DE69422265T2 (de) 1993-10-28 1994-10-14 Verfahren zur Herstellung einer strahlungsgeschützten Silizium-auf-Isolator Halbleiteranordnung

Country Status (3)

Country Link
US (1) US5360752A (de)
EP (1) EP0652591B1 (de)
DE (1) DE69422265T2 (de)

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EP0564204A3 (en) * 1992-03-30 1994-09-28 Mitsubishi Electric Corp Semiconductor device
US5786236A (en) * 1996-03-29 1998-07-28 Eastman Kodak Company Backside thinning using ion-beam figuring
US5795813A (en) * 1996-05-31 1998-08-18 The United States Of America As Represented By The Secretary Of The Navy Radiation-hardening of SOI by ion implantation into the buried oxide layer
KR100232886B1 (ko) * 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
US6337500B1 (en) * 1997-06-19 2002-01-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6054369A (en) * 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
US6362075B1 (en) * 1999-06-30 2002-03-26 Harris Corporation Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
US6368938B1 (en) 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
US6287901B1 (en) 2000-01-05 2001-09-11 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US6642085B1 (en) 2000-11-03 2003-11-04 The Regents Of The University Of California Thin film transistors on plastic substrates with reflective coatings for radiation protection
US6638832B2 (en) 2000-12-21 2003-10-28 Bae Systems Information And Electronic Systems Integration, Inc. Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices
US6531739B2 (en) * 2001-04-05 2003-03-11 Peregrine Semiconductor Corporation Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
US7411250B2 (en) * 2001-04-05 2008-08-12 Peregrine Semiconductor Corporation Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
US6737337B1 (en) * 2001-04-27 2004-05-18 Advanced Micro Devices, Inc. Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device
US6509613B1 (en) 2001-05-04 2003-01-21 Advanced Micro Devices, Inc. Self-aligned floating body control for SOI device through leakage enhanced buried oxide
US6512244B1 (en) 2001-05-07 2003-01-28 Advanced Micro Devices, Inc. SOI device with structure for enhancing carrier recombination and method of fabricating same
US7122863B1 (en) * 2001-05-07 2006-10-17 Advanced Micro Devices, Inc. SOI device with structure for enhancing carrier recombination and method of fabricating same
US6602757B2 (en) * 2001-05-21 2003-08-05 International Business Machines Corporation Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI
US7736915B2 (en) * 2006-02-21 2010-06-15 International Business Machines Corporation Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure
JP2007273919A (ja) 2006-03-31 2007-10-18 Nec Corp 半導体装置及びその製造方法
DE102007036147B4 (de) * 2007-08-02 2017-12-21 Infineon Technologies Austria Ag Verfahren zum Herstellen eines Halbleiterkörpers mit einer Rekombinationszone
US20100019351A1 (en) * 2008-07-28 2010-01-28 Albert Ratnakumar Varactors with enhanced tuning ranges
US7943482B2 (en) * 2008-08-06 2011-05-17 International Business Machines Corporation Method for semiconductor device having radiation hardened insulators and design structure thereof
US7935609B2 (en) * 2008-08-06 2011-05-03 International Business Machines Corporation Method for fabricating semiconductor device having radiation hardened insulators
RU2497231C1 (ru) * 2012-04-19 2013-10-27 Федеральное государственное бюджетное учреждение науки Институт физики полупроводников им. А.В. Ржанова Сибирского отделения Российской академии наук (ИФП СО РАН) Способ изготовления структуры кремний-на-изоляторе
RU2498450C1 (ru) * 2012-04-26 2013-11-10 Федеральное государственное бюджетное учреждение науки Институт физики полупроводников им. А.В. Ржанова Сибирского отделения Российской академии наук (ИФП СО РАН) Способ изготовления структуры полупроводник-на-изоляторе
US8518807B1 (en) 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
CN103367450B (zh) * 2013-05-09 2016-02-17 北京大学 一种抗辐射加固的soi器件及其制备方法
JP7348062B2 (ja) 2016-12-23 2023-09-20 ボード オブ リージェンツ，ザ ユニバーシティ オブ テキサス システム モアレベース計測学及び真空ベースピックアンドプレースを用いたコンパクト装置へのコンポーネントのヘテロジニアスインテグレーション

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US3935033A (en) * 1970-07-18 1976-01-27 Siemens Aktiengesellschaft Method of improving the radiation resistance of silicon transistors with a silicon oxide coating
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
US4634473A (en) * 1985-09-09 1987-01-06 Rca Corporation Method for fabricating a radiation hardened oxide having structural damage
NL8701251A (nl) * 1987-05-26 1988-12-16 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US4965213A (en) * 1988-02-01 1990-10-23 Texas Instruments Incorporated Silicon-on-insulator transistor with body node to source node connection
US5021359A (en) * 1988-06-21 1991-06-04 Harris Corporation Radiation hardened complementary transistor integrated circuits
JPH02144925A (ja) * 1988-11-26 1990-06-04 Nec Corp 半導体装置
EP0378906A1 (de) * 1988-12-08 1990-07-25 Fujitsu Limited Verfahren zur Herstellung einer Halbleiter-auf-Isolator-Struktur und Halbleiterbauelement, das die Halbleiter-auf-Isolator-Struktur enthält
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5024965A (en) * 1990-02-16 1991-06-18 Chang Chen Chi P Manufacturing high speed low leakage radiation hardened CMOS/SOI devices
JPH0411736A (ja) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5137837A (en) * 1990-08-20 1992-08-11 Hughes Aircraft Company Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate
US5185280A (en) * 1991-01-29 1993-02-09 Texas Instruments Incorporated Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
JPH05136259A (ja) * 1991-11-12 1993-06-01 Hitachi Ltd 半導体基板及び半導体装置

Also Published As

Publication number Publication date
EP0652591B1 (de) 1999-12-22
US5360752A (en) 1994-11-01
EP0652591A1 (de) 1995-05-10
DE69422265T2 (de) 2000-07-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INT