DE69722661D1 - Verfahren zur herstellung einer halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung

Info

Publication number
DE69722661D1
DE69722661D1 DE69722661T DE69722661T DE69722661D1 DE 69722661 D1 DE69722661 D1 DE 69722661D1 DE 69722661 T DE69722661 T DE 69722661T DE 69722661 T DE69722661 T DE 69722661T DE 69722661 D1 DE69722661 D1 DE 69722661D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69722661T
Other languages
English (en)
Other versions
DE69722661T2 (de
Inventor
Tsukasa Shiraishi
Yoshihiro Bessho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69722661D1 publication Critical patent/DE69722661D1/de
Application granted granted Critical
Publication of DE69722661T2 publication Critical patent/DE69722661T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/818—Bonding techniques
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
DE69722661T 1996-03-06 1997-03-05 Verfahren zur herstellung einer halbleitervorrichtung Expired - Fee Related DE69722661T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8049065A JP2951882B2 (ja) 1996-03-06 1996-03-06 半導体装置の製造方法及びこれを用いて製造した半導体装置
JP4906596 1996-03-06
PCT/JP1997/000672 WO1997033313A1 (fr) 1996-03-06 1997-03-05 Dispositif a semi-conducteur et son procede de production

Publications (2)

Publication Number Publication Date
DE69722661D1 true DE69722661D1 (de) 2003-07-10
DE69722661T2 DE69722661T2 (de) 2004-05-13

Family

ID=12820690

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69722661T Expired - Fee Related DE69722661T2 (de) 1996-03-06 1997-03-05 Verfahren zur herstellung einer halbleitervorrichtung

Country Status (7)

Country Link
US (1) US6452280B1 (de)
EP (2) EP0951063B1 (de)
JP (1) JP2951882B2 (de)
KR (1) KR100300758B1 (de)
CN (1) CN1175480C (de)
DE (1) DE69722661T2 (de)
WO (1) WO1997033313A1 (de)

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US6940178B2 (en) * 2001-02-27 2005-09-06 Chippac, Inc. Self-coplanarity bumping shape for flip chip
TWI245395B (en) * 2001-11-20 2005-12-11 Advanced Semiconductor Eng Multi-chip module package device
CN100356559C (zh) * 2003-09-24 2007-12-19 财团法人工业技术研究院 倒装芯片封装结构及其制造方法
TWI273664B (en) * 2004-03-26 2007-02-11 Advanced Semiconductor Eng Bumping process, bump structure, packaging process and package structure
KR100696190B1 (ko) * 2004-12-14 2007-03-20 한국전자통신연구원 플립 칩 본딩방법
JP4325571B2 (ja) * 2005-02-28 2009-09-02 株式会社日立製作所 電子装置の製造方法
TWI253697B (en) * 2005-04-08 2006-04-21 Phoenix Prec Technology Corp Method for fabricating a flip chip package
JP4765804B2 (ja) * 2006-07-14 2011-09-07 株式会社デンソー 半導体装置の製造方法
JP2008135719A (ja) * 2006-10-31 2008-06-12 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2008218643A (ja) * 2007-03-02 2008-09-18 Fujitsu Ltd 半導体装置及びその製造方法
US8309864B2 (en) * 2008-01-31 2012-11-13 Sanyo Electric Co., Ltd. Device mounting board and manufacturing method therefor, and semiconductor module
JP5028291B2 (ja) * 2008-01-31 2012-09-19 三洋電機株式会社 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法
JP5385004B2 (ja) * 2009-05-22 2014-01-08 富士通テン株式会社 回路部品
JP6143104B2 (ja) * 2012-12-05 2017-06-07 株式会社村田製作所 バンプ付き電子部品及びバンプ付き電子部品の製造方法
KR102248876B1 (ko) * 2014-12-24 2021-05-07 엘지디스플레이 주식회사 표시장치 어레이 기판 및 표시장치

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JPH02177546A (ja) * 1988-12-28 1990-07-10 Fujitsu Ltd 半導体集積回路の製造方法
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KR19990087563A (ko) 1999-12-27
CN1175480C (zh) 2004-11-10
JP2951882B2 (ja) 1999-09-20
EP0951063A4 (de) 1999-10-20
EP0951063B1 (de) 2003-06-04
WO1997033313A1 (fr) 1997-09-12
EP1191578A3 (de) 2002-05-08
EP1191578A2 (de) 2002-03-27
EP0951063A1 (de) 1999-10-20
KR100300758B1 (ko) 2001-11-02
CN1212786A (zh) 1999-03-31
JPH09246320A (ja) 1997-09-19
DE69722661T2 (de) 2004-05-13
US6452280B1 (en) 2002-09-17

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