KR950034602A - 반도체장치의 다층배선 형성방법 - Google Patents

반도체장치의 다층배선 형성방법 Download PDF

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Publication number
KR950034602A
KR950034602A KR1019940009654A KR19940009654A KR950034602A KR 950034602 A KR950034602 A KR 950034602A KR 1019940009654 A KR1019940009654 A KR 1019940009654A KR 19940009654 A KR19940009654 A KR 19940009654A KR 950034602 A KR950034602 A KR 950034602A
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South Korea
Prior art keywords
forming
dielectric layer
photoresist
layer
multilayer wiring
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KR1019940009654A
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English (en)
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KR0124638B1 (ko
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박내학
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문정환
금성일렉트론 주식회사
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Priority to KR1019940009654A priority Critical patent/KR0124638B1/ko
Publication of KR950034602A publication Critical patent/KR950034602A/ko
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Publication of KR0124638B1 publication Critical patent/KR0124638B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 다층배선 형성방법에 관한 것으로 특히, 고집적 다층배선 소자에 적당하도록 한 금속매립형의 아이엠디(IMD)평탄화 기술에 관한 것이다.
이를 위해, 본 발명은 반도체기판상에 제1유전체층을 형성하고 상기 제1유전체 층상의 소정영역에 제1도전층을 형성하는 공정과, 전면에 제2유전체층을 형성하는 공정과, 전면에 제1포토 레지스트를 형성하고 노광 및 현상으로 형성하고자 하는 배선 패턴으로 패턴닝하는 공정과, 상기 제1포토 레지스트를 마스크로 하여 제2유전체층을 소정 깊이로 선택적 식각하는 공정과, 전면에 제2포토 레지스트를 형성하고 노광 및 현상으로 형성하고자 하는 배선콘택 패턴을 패턴닝하는 공정과, 상기 제2포토 레지스트를 마스크로 하여 제2유전체층을 선택적으로 하여 제1도전층에 콘택홀을 형성하는 공정과, 전면에 제2도전층을 형성하고 에치백하여 다층배선을 완성하는 공정으로 이루어짐을 특징으로 한다.
이와 같이 상술한 본 발명의 반도채장치의 다층배선 형성방법은 선택비가 같은 포토레지스트를 사용하므로 공정단순화가 가능하며 오차의 발생을 줄이는 효과가 있다.

Description

반도체장치의 다층배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 반도체장치의 다층배선 형성방법을 나타낸 공정순서 단면도.

Claims (3)

  1. 반도체기판상에 제1유전체층을 형성하고 상기 제1유전체층상의 소정영역에 제1도전층을 형성하는 공정과, 전면에 제2유전체층을 형성하는 공정과, 전면에 제1포토 레지스트를 형성하고 노광 및 현상으로 형성하고자 하는 배선 패턴으로 패턴닝하는 공정과, 상기 제1포토 레지스트를 마스크로 하여 제2유전체층을 소정 깊이로 선택적 식각하는 공정과, 전면에 제2포토 레지스트를 형성하고 노광 및 현상으로 형성하고자 하는 배선콘택 패턴을 패턴닝하는 공정과, 상기 제2포토 레지스트를 마스크로 하여 제2유전체층을 선택적으로 하여 제1도전층에 콘택홀을 형성하는 공정과, 전면에 제2도전층을 형성하고 에치백하여 다층배선을 완성하는 공정으로 이루어짐을 특징으로 한는 반도체장치의 다층배선 형성방법.
  2. 제1항에 있어서, 상기 제1유전체층은 아이엘디(ILD)층으로 형성함을 특징으로 하는 반도체장치의 다층배선 형성방법.
  3. 제1항에 있어서, 상기 제2유전체층은 아이엘디(ILD)층으로 형성함을 특징으로 하는 반도체장치의 다층배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940009654A 1994-05-02 1994-05-02 반도체장치의 다층배선 형성방법 KR0124638B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940009654A KR0124638B1 (ko) 1994-05-02 1994-05-02 반도체장치의 다층배선 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940009654A KR0124638B1 (ko) 1994-05-02 1994-05-02 반도체장치의 다층배선 형성방법

Publications (2)

Publication Number Publication Date
KR950034602A true KR950034602A (ko) 1995-12-28
KR0124638B1 KR0124638B1 (ko) 1997-12-11

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418920B1 (ko) * 1997-12-15 2004-05-20 주식회사 하이닉스반도체 반도체소자의배선형성방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459062B1 (ko) * 2001-12-28 2004-12-03 동부전자 주식회사 반도체 제조 공정에서의 콘택트 홀 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418920B1 (ko) * 1997-12-15 2004-05-20 주식회사 하이닉스반도체 반도체소자의배선형성방법

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