KR960026270A - 콘택홀 형성방법 - Google Patents

콘택홀 형성방법 Download PDF

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Publication number
KR960026270A
KR960026270A KR1019940033687A KR19940033687A KR960026270A KR 960026270 A KR960026270 A KR 960026270A KR 1019940033687 A KR1019940033687 A KR 1019940033687A KR 19940033687 A KR19940033687 A KR 19940033687A KR 960026270 A KR960026270 A KR 960026270A
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KR
South Korea
Prior art keywords
forming
pattern
conductive layer
contact hole
insulating layer
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Application number
KR1019940033687A
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English (en)
Other versions
KR100291825B1 (ko
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940033687A priority Critical patent/KR100291825B1/ko
Publication of KR960026270A publication Critical patent/KR960026270A/ko
Application granted granted Critical
Publication of KR100291825B1 publication Critical patent/KR100291825B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 고집적 반도체소자의 콘택홀 형성방법에 관한 것으로, 도전층패턴을 형성할때 콘택홀을 함께 형성함으로 인하여 공정스텝을 감소시키고 도전층패턴과의 간격을 최소화하여 고집적화에 기여할 수 있는 기술이다.

Description

콘택홀 형성방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도 내지 제9도는 본 발명의 실시예에 의한 반도체소자의 콘택홀 형성단계를 도시한 단면도.

Claims (4)

  1. 반도체소자의 콘택홀 형성방법에 있어서, 반도체기판상부에 제1절연층, 도전층을 적층하고 그 상부에 제1감광막패턴을 형성하는 단계와, 노출된 도전층을 식각하여 분리되지 않은 도전층패턴을 형성하고, 상기 제1감광막패턴을 제거하는 단계와, 전체적으로 제2절연층을 형성하고 제2감광막패턴을 형성하는 단계와, 제2감광막패턴을 마스크로 이용하여 노출된 지역의 제2절연층과 도전층패턴, 제1절연층을 식각하여 두개로 분리된 도전층패턴과 반도체기판이 노출되는 콘택홀을 형성하는 단계와, 상기 제2감광막패턴을 제거하고 상기 콘택홀 측벽에 제3절연층 스페이서를 형성하는 단계를 포함하는 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 제1감광막패턴은 콘택홀과 두개의 도전층패턴이 형성되는 지역을 도포하도록 형성되는 것을 특징으로 하는 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 두개로 분리된 도전층패턴과 도전층패턴 사이의 거리는 광 리소그라피공정으로 형성할 수 있는 최소패턴으로 형성하는 것을 특징으로 하는 콘택홀 형성방법.
  4. 제1항에 있어서, 상기 제3절연층 스페이서는 전체구조 상부에 도포된 제3절연층을 블란켓 식각하여 상기 콘택홀 측벽에만 형성하는 것을 특징으로 하는 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940033687A 1994-12-12 1994-12-12 콘택홀형성방법 KR100291825B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940033687A KR100291825B1 (ko) 1994-12-12 1994-12-12 콘택홀형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940033687A KR100291825B1 (ko) 1994-12-12 1994-12-12 콘택홀형성방법

Publications (2)

Publication Number Publication Date
KR960026270A true KR960026270A (ko) 1996-07-22
KR100291825B1 KR100291825B1 (ko) 2001-12-01

Family

ID=37526130

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940033687A KR100291825B1 (ko) 1994-12-12 1994-12-12 콘택홀형성방법

Country Status (1)

Country Link
KR (1) KR100291825B1 (ko)

Also Published As

Publication number Publication date
KR100291825B1 (ko) 2001-12-01

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