KR890011059A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR890011059A
KR890011059A KR1019870015349A KR870015349A KR890011059A KR 890011059 A KR890011059 A KR 890011059A KR 1019870015349 A KR1019870015349 A KR 1019870015349A KR 870015349 A KR870015349 A KR 870015349A KR 890011059 A KR890011059 A KR 890011059A
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KR
South Korea
Prior art keywords
insulating film
substrate
forming
manufacturing
semiconductor device
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Application number
KR1019870015349A
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English (en)
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KR910000277B1 (ko
Inventor
이윤진
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870015349A priority Critical patent/KR910000277B1/ko
Publication of KR890011059A publication Critical patent/KR890011059A/ko
Application granted granted Critical
Publication of KR910000277B1 publication Critical patent/KR910000277B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도는 본 발명에 따른 반도체 장치의 레이아웃 평면도.
제 3(A)-(D)도는 본 발명에 따른 제조공정도.

Claims (4)

  1. 반도체 장치의 제조방법에 있어서, 반도체 기판상의 제1 절연막상에 상기 반도체 기판에 형성된 소자의 소정부분과 접속을 하기 위한 제1 도전막을 형성하는 제1공정과, 상기 제1도전막상에 제2절연막을 도포하고 제1절연막과 제1도전막을 함께 패터닝하는 제2공정과, 기판상에 제3절연막을 도포하는 제3공정과, 접속창 형성을 위하여 기판상에 접속창 영역보다 넓은 접속창 마스크를 형성하는 제4공정과, 상기 접속창 마스크를 식각 마스크로 하여 접속창 영역을 식각하는 제5공정과, 상기 접속창 마스크를 제거하고 기판상에 제2도전막을 형성하는 제6공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.
  2. 제 1 항에 있어서, 제 2 절연막을 제 1 절연막보다 충분히 두꺼운 두께의 절연산화막임을 특징으로 하는 반도체 장치의 제조방법.
  3. 반도체 장치의 제조방법에 있어서, 반도체 기판상의 제1 절연막상에 상기 반도체 기판에 형성된 소자의 소정부분과 접속을 하기 위한 제1 도전막을 형성하는 제1공정과, 상기 제1 도전막 상부와 측면에 제2절연막을 형성하는 제2공정과, 기판상에 제3절연막을 도포하는 제3공정과, 접속창 형성을 위하여 기판상에 접속창 영역보다 넓은 접속창 마스크를 형성하는 제4공정과, 상기 접속창 마스크를 식각 마스크로 하여 접속창 영역을 식각하는 제5공정과, 상기 접속창 마스크를 제거하고 기판상에 제2도전막을 형성하는 제6공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.
  4. 제 3 항에 있어서, 제 2 절연막이 제 1 절연막보다 충분히 두꺼운 두께의 절연산화막임을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870015349A 1987-12-30 1987-12-30 반도체 장치의 제조방법 KR910000277B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870015349A KR910000277B1 (ko) 1987-12-30 1987-12-30 반도체 장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870015349A KR910000277B1 (ko) 1987-12-30 1987-12-30 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR890011059A true KR890011059A (ko) 1989-08-12
KR910000277B1 KR910000277B1 (ko) 1991-01-23

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ID=19267653

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870015349A KR910000277B1 (ko) 1987-12-30 1987-12-30 반도체 장치의 제조방법

Country Status (1)

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Also Published As

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KR910000277B1 (ko) 1991-01-23

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