KR920017236A - 폴리실리콘층을 이용한 자기정렬콘택 제조방법 - Google Patents

폴리실리콘층을 이용한 자기정렬콘택 제조방법 Download PDF

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Publication number
KR920017236A
KR920017236A KR1019910003273A KR910003273A KR920017236A KR 920017236 A KR920017236 A KR 920017236A KR 1019910003273 A KR1019910003273 A KR 1019910003273A KR 910003273 A KR910003273 A KR 910003273A KR 920017236 A KR920017236 A KR 920017236A
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KR
South Korea
Prior art keywords
self
polysilicon layer
insulating
oxide film
film
Prior art date
Application number
KR1019910003273A
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English (en)
Other versions
KR950000519B1 (ko
Inventor
손곤
이헌철
윤수식
이동덕
박해성
김세정
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910003273A priority Critical patent/KR950000519B1/ko
Priority to US07/842,549 priority patent/US5264391A/en
Publication of KR920017236A publication Critical patent/KR920017236A/ko
Application granted granted Critical
Publication of KR950000519B1 publication Critical patent/KR950000519B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

폴리실리콘층을 이용한 자기정렬콘택 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 의해 보호막용 폴리실리콘층을 이용한 자기정렬콘택 형성단계를 도시한 도면.

Claims (1)

  1. 실리콘 기판 상부에 게이트 산화막, 폴리실리콘층 및 절연산화막을 순차적으로 적층한 다음, 게이트전극마스크 공정으로 소정부분 제거하여 다수의 게이트 전극을 형성하고, 전체적으로 절연막을 형성한 다음 상기 게이트전극 사이의 절연막을 식각하여 자기정렬된 콘택홀을 형성하고, 도전층을 콘택시키는 자기정렬된 제조방법에 있어서, 상기 절연막을 식각하여 자기정렬된 콘택홀을 형성할때에 게이트전극 상부의 절연산화막이 손상되는 것을 방지하기 위하여 상기 절연산화막 상부에 상기 절연산화막에 대하여 식각선택비가 높은 보호막용 폴리실콘층을 예정된 콘택영역보다 조금 넓게 형성하는 단계와, 게이트 전극마스크 공정으로 절연산화막 상부에 국부적인 보호막용 폴리실리콘층이 형성된 다수의 게이트 전극을 형성하는 단계와 상기 다수의 게이트 전극을 포함하는 구조전체 상부에 절연막을 형성하고 예정된 콘택영역의 절연막 및 게이트 산화막을 식각하여 상기 국부적인 폴리실리콘층의 일부 및 게이트전극 사이의 실리콘 기판이 노출되도록 하는 단계와, 도전층을 상기 노출된 실리콘 기판에 콘택하는 단계로 이루어지는 것을 특징으로 하는 폴리실리콘을 이용한 자기정렬콘택 제조방법.
    ※참고사항:최초출원 내용에 의하여 공개되는 것임.
KR1019910003273A 1991-02-28 1991-02-28 폴리실리콘층을 이용한 자기정렬콘택 제조방법 KR950000519B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910003273A KR950000519B1 (ko) 1991-02-28 1991-02-28 폴리실리콘층을 이용한 자기정렬콘택 제조방법
US07/842,549 US5264391A (en) 1991-02-28 1992-02-27 Method of forming a self-aligned contact utilizing a polysilicon layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910003273A KR950000519B1 (ko) 1991-02-28 1991-02-28 폴리실리콘층을 이용한 자기정렬콘택 제조방법

Publications (2)

Publication Number Publication Date
KR920017236A true KR920017236A (ko) 1992-09-26
KR950000519B1 KR950000519B1 (ko) 1995-01-24

Family

ID=19311607

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910003273A KR950000519B1 (ko) 1991-02-28 1991-02-28 폴리실리콘층을 이용한 자기정렬콘택 제조방법

Country Status (2)

Country Link
US (1) US5264391A (ko)
KR (1) KR950000519B1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377139A (en) * 1992-12-11 1994-12-27 Motorola, Inc. Process forming an integrated circuit
KR970009617B1 (en) * 1993-12-31 1997-06-14 Hyundai Electronics Ind Contact forming method of semiconductor device
JPH08321545A (ja) * 1995-05-24 1996-12-03 Yamaha Corp 配線形成法
US5686357A (en) * 1995-07-10 1997-11-11 Micron Technology, Inc. Method for forming a contact during the formation of a semiconductor device
US6066555A (en) * 1995-12-22 2000-05-23 Cypress Semiconductor Corporation Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning
US5723374A (en) * 1996-12-27 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming dielectric spacer to prevent poly stringer in stacked capacitor DRAM technology
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
US4839305A (en) * 1988-06-28 1989-06-13 Texas Instruments Incorporated Method of making single polysilicon self-aligned transistor
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
US5114879A (en) * 1990-11-30 1992-05-19 Texas Instruments Incorporated Method of forming a microelectronic contact

Also Published As

Publication number Publication date
US5264391A (en) 1993-11-23
KR950000519B1 (ko) 1995-01-24

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