KR930009050A - 반도체 집적 회로 장치 및 그 제조 방법 - Google Patents
반도체 집적 회로 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR930009050A KR930009050A KR1019920018793A KR920018793A KR930009050A KR 930009050 A KR930009050 A KR 930009050A KR 1019920018793 A KR1019920018793 A KR 1019920018793A KR 920018793 A KR920018793 A KR 920018793A KR 930009050 A KR930009050 A KR 930009050A
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- South Korea
- Prior art keywords
- insulating film
- containing boron
- forming
- bed layer
- film containing
- Prior art date
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Abstract
패드 베드를 용이하게 형성함과 동시에 본딩 패드부에서의 막의 박리를 방지하기 위해 패드 베드를 보호함으로써 절연막에 대한 부착력을 향상시킨 반도체 집적 회로 장치 및 그 제조방법을 제공한다. 붕소를 포함하는 BPSG 절연막(4)에 형성한 접속 구멍내에 형성된 접속 플러그 및 배선의 본딩 패드부(30)아래 형성된 패드 베드를 3층으로 형성된 폴리실리콘막(7,8및9)로 형성함으로써 공정의 증가를 억제할 수 있다. 패드 베드에 보호막을 설치할 수도 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 단면도
제2도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도
제3도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도
제4도는 본 발명의 제2실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도
Claims (12)
- 반도체 기판(1), 상기 반도체 기판 상에 형성된 붕소를 포함하는 절연막(4), 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층(5), 상기 붕소를 포함하는 절연막에 형성된 접속 구멍(6), 상기 접속 구멍 내에 매설되고 적어도 일부가 상기 패드 베드층과 동일한 재료로 이루어지는 접속 플러그(23) 및 상기 붕소를 포함하는 절연막상에 형성되어 상기 패드 베드층상에 배치되어 있는 본딩 패드부(30)을 가지고 상기 접촉 플러그와 접촉해 있는 배선(10,11및12)를 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
- 제1항에 있어서, 상기 패드 베드층 아래에 배치하도록 상기 붕소를 포함하는 절연막에 버퍼층(20)을 매설한 것을 특징으로 하는 반도체 집적 회로 장치.
- 제1항에 있어서, 상기 배선이 붕소와 반응하여 안정한 생성물을 형성하는 재료로 구성되거나 또는 그 최하층이 상기 재료로 이루어지는 2층 이상의 적층 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
- 제4항에 있어서, 상기 패드 베드층이 폴리실리콘, W나 MO 등의 고융점 금속, 상기 고융점 금속의 규화물, 상기 고융점 금속의 질화물, Cu, Al에서 선택되거나 또는 이들을 적층하여 이루어지는 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
- 반도체 기판(1), 상기 반도체 기판 상에 형성된 붕소를 포함하는 절연막(4), 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층(5), 상기 패드 베드층을 피복하는 피복막(22,26및27), 상기 붕소를 포함하는 절연막에 형성된 접속 구멍(6), 상기 접속 구멍 내에 매설된 접속 플러그(23) 및 상기 붕소를 포함하는 절연막상에 형성되고 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선(12 및 25)를 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
- 제5항에 있어서, 상기 배선이 붕소와 반응하여 안정한 생성물을 형성하는 재료로 구성되거나 또는 그 최하층이 상기 재료로 이루어지는 2층 이상의 적층 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
- 제5항에 있어서, 상기 패드 베드층이 폴리실리콘, W나 MO 등의 고융점 금속, 상기 고융점 금속의 규화물, 상기 고융점 금속의 질화물, Cu, Al에서 선택되거나 또는 이들을 적층하여 이루어지는 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
- 제5항에 있어서, 상기 패드 베드층 아래에 배치하도록 상기 붕소를 포함하는 절연막에 버퍼층을 매설한 것을 특징으로 하는 반도체 집적 회로 장치.
- 반도체 기판 상에 형성된 붕소를 포함하는 절연막을 형성하는 공정, 상기 붕소를 포함하는 절연막에 접속 구멍을 형성하는 공정, 상기 붕소를 포함하는 절연막 전면에 도전막을 형성하고, 이 도전막을 에칭함으로써 상기 붕소를 절연막상 또는 절연막에 설치한 홈 내 및 상기 접속 구멍 내에 각각 패드 베드층과 접속 플러그을 형성하는 공정 및 상기 붕소를 포함하는 절연막상에 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉하는 배선을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
- 반도체 기판 상에 형성된 붕소를 포함하는 절연막을 형성하는 공정, 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층을 형성하는 공정, 상기 패드 베드층을 피복하는 피복막을 형성하는 공정, 상기 붕소를 포함하는 절연막에 형성된 접속 구멍을 형성하는 공정, 상기 접속 구멍 내에 접속 플러그를 매설하는 공정 및 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선을 상기 붕소를 포함하는 절연막상에 형성하는 공정을 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
- 제10항에 있어서, 상기 피복막이 접속 플러그를 형성한 후 적어도 일부는 패드 베드 층상에서 제거해 버리는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
- 반도체 기판에 도전막을 형성해서 이 도전막을 에칭함으로써 이 반도체 기판의 소자 영역에 배치된 게이트 전극과 버퍼층을 형성하는 공정, 상기 반도체 기판에 붕소를 포함하는 절연막을 형성하여 상기 게이트 전극과 상기 버퍼를 절연막에 매설하는 공정, 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내 또는 절연막에 관통 구멍을 형성하여 이 관통 구멍내에서 상기 버퍼층과 직접 접하도록 패드 베드층을 형성하는 공정, 상기 붕소를 포함하는 절연막에 접속 구멍을 형성하는 공정, 상기 접속 구멍 내에 접속 플러그를 매설하는 공정 및 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선을 상기 붕소를 포함하는 절연막상에 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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JP3291873A JP2550248B2 (ja) | 1991-10-14 | 1991-10-14 | 半導体集積回路装置およびその製造方法 |
JP91-291873 | 1991-11-14 |
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JP3587537B2 (ja) * | 1992-12-09 | 2004-11-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US5798287A (en) * | 1993-12-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Method for forming a power MOS device chip |
EP0660402B1 (en) * | 1993-12-24 | 1998-11-04 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Power semiconductor device |
DE69321965T2 (de) * | 1993-12-24 | 1999-06-02 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | MOS-Leistungs-Chip-Typ und Packungszusammenbau |
JPH07193024A (ja) * | 1993-12-27 | 1995-07-28 | Nec Corp | 半導体装置およびその製造方法 |
JP2833989B2 (ja) * | 1993-12-30 | 1998-12-09 | 日本電気株式会社 | 半導体装置の製造方法 |
US6750091B1 (en) * | 1996-03-01 | 2004-06-15 | Micron Technology | Diode formation method |
US5827762A (en) * | 1997-05-02 | 1998-10-27 | National Semiconductor Corporation | Method for forming buried interconnect structue having stability at high temperatures |
KR100475734B1 (ko) * | 1997-10-14 | 2005-06-23 | 삼성전자주식회사 | 와이어본딩충격에대한완충특성을갖는반도체장치의패드및그제조방법 |
JPH11121458A (ja) | 1997-10-21 | 1999-04-30 | Nec Kyushu Ltd | 半導体装置 |
WO1999038204A1 (fr) * | 1998-01-23 | 1999-07-29 | Rohm Co., Ltd. | Interconnexion damasquinee et dispositif a semi-conducteur |
JP3269475B2 (ja) * | 1998-02-16 | 2002-03-25 | 日本電気株式会社 | 半導体装置 |
JPH11261010A (ja) * | 1998-03-13 | 1999-09-24 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6218732B1 (en) * | 1998-09-15 | 2001-04-17 | Texas Instruments Incorporated | Copper bond pad process |
TW445616B (en) * | 1998-12-04 | 2001-07-11 | Koninkl Philips Electronics Nv | An integrated circuit device |
JP2000269293A (ja) * | 1999-03-18 | 2000-09-29 | Fujitsu Ltd | 半導体装置 |
US7388289B1 (en) * | 1999-09-02 | 2008-06-17 | Micron Technology, Inc. | Local multilayered metallization |
AU2001286453A1 (en) * | 2000-08-11 | 2002-02-25 | Chem Trace Corporation | System and method for cleaning semiconductor fabrication equipment parts |
US6593221B1 (en) * | 2002-08-13 | 2003-07-15 | Micron Technology, Inc. | Selective passivation of exposed silicon |
US7091132B2 (en) * | 2003-07-24 | 2006-08-15 | Applied Materials, Inc. | Ultrasonic assisted etch using corrosive liquids |
US7045072B2 (en) * | 2003-07-24 | 2006-05-16 | Tan Samantha S H | Cleaning process and apparatus for silicate materials |
US7754609B1 (en) | 2003-10-28 | 2010-07-13 | Applied Materials, Inc. | Cleaning processes for silicon carbide materials |
KR100675275B1 (ko) * | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | 반도체 장치 및 이 장치의 패드 배치방법 |
JP4944402B2 (ja) | 2005-07-13 | 2012-05-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR101432161B1 (ko) * | 2006-11-01 | 2014-08-20 | 퀀텀 글로벌 테크놀로지스, 엘엘씨 | 챔버 부품을 세정하기 위한 방법 및 장치 |
WO2011156787A2 (en) * | 2010-06-11 | 2011-12-15 | Crossbar, Inc. | Pillar structure for memory device and method |
JP2016115698A (ja) * | 2014-12-11 | 2016-06-23 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
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JPS5331965A (en) * | 1976-09-06 | 1978-03-25 | Nec Corp | Electrode structure of semiconductor device |
JPS57113235A (en) * | 1980-12-29 | 1982-07-14 | Nec Corp | Semiconductor device |
JPS615561A (ja) * | 1984-06-20 | 1986-01-11 | Hitachi Ltd | 半導体装置 |
JPH0727921B2 (ja) * | 1987-07-31 | 1995-03-29 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH07114214B2 (ja) * | 1987-08-03 | 1995-12-06 | 三菱電機株式会社 | 半導体装置 |
JPS6461735A (en) * | 1987-09-01 | 1989-03-08 | Fujitsu Ltd | Arrangement structure of progressive wave type optical amplifier |
-
1991
- 1991-10-14 JP JP3291873A patent/JP2550248B2/ja not_active Expired - Fee Related
-
1992
- 1992-10-13 KR KR1019920018793A patent/KR960005558B1/ko not_active IP Right Cessation
- 1992-10-13 US US07/959,644 patent/US5365112A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JPH05335370A (ja) | 1993-12-17 |
KR960005558B1 (ko) | 1996-04-26 |
US5365112A (en) | 1994-11-15 |
JP2550248B2 (ja) | 1996-11-06 |
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