KR930009050A - 반도체 집적 회로 장치 및 그 제조 방법 - Google Patents

반도체 집적 회로 장치 및 그 제조 방법 Download PDF

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Publication number
KR930009050A
KR930009050A KR1019920018793A KR920018793A KR930009050A KR 930009050 A KR930009050 A KR 930009050A KR 1019920018793 A KR1019920018793 A KR 1019920018793A KR 920018793 A KR920018793 A KR 920018793A KR 930009050 A KR930009050 A KR 930009050A
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South Korea
Prior art keywords
insulating film
containing boron
forming
bed layer
film containing
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KR1019920018793A
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English (en)
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KR960005558B1 (ko
Inventor
요이찌 오시마
Original Assignee
사또 후미오
가부시끼가이샤 도시바
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Publication of KR930009050A publication Critical patent/KR930009050A/ko
Application granted granted Critical
Publication of KR960005558B1 publication Critical patent/KR960005558B1/ko

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Abstract

패드 베드를 용이하게 형성함과 동시에 본딩 패드부에서의 막의 박리를 방지하기 위해 패드 베드를 보호함으로써 절연막에 대한 부착력을 향상시킨 반도체 집적 회로 장치 및 그 제조방법을 제공한다. 붕소를 포함하는 BPSG 절연막(4)에 형성한 접속 구멍내에 형성된 접속 플러그 및 배선의 본딩 패드부(30)아래 형성된 패드 베드를 3층으로 형성된 폴리실리콘막(7,8및9)로 형성함으로써 공정의 증가를 억제할 수 있다. 패드 베드에 보호막을 설치할 수도 있다.

Description

반도체 집적 회로 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 단면도
제2도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도
제3도는 본 발명의 제1실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도
제4도는 본 발명의 제2실시예에 관한 반도체 집적 회로 장치의 제조 공정 단면도

Claims (12)

  1. 반도체 기판(1), 상기 반도체 기판 상에 형성된 붕소를 포함하는 절연막(4), 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층(5), 상기 붕소를 포함하는 절연막에 형성된 접속 구멍(6), 상기 접속 구멍 내에 매설되고 적어도 일부가 상기 패드 베드층과 동일한 재료로 이루어지는 접속 플러그(23) 및 상기 붕소를 포함하는 절연막상에 형성되어 상기 패드 베드층상에 배치되어 있는 본딩 패드부(30)을 가지고 상기 접촉 플러그와 접촉해 있는 배선(10,11및12)를 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
  2. 제1항에 있어서, 상기 패드 베드층 아래에 배치하도록 상기 붕소를 포함하는 절연막에 버퍼층(20)을 매설한 것을 특징으로 하는 반도체 집적 회로 장치.
  3. 제1항에 있어서, 상기 배선이 붕소와 반응하여 안정한 생성물을 형성하는 재료로 구성되거나 또는 그 최하층이 상기 재료로 이루어지는 2층 이상의 적층 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
  4. 제4항에 있어서, 상기 패드 베드층이 폴리실리콘, W나 MO 등의 고융점 금속, 상기 고융점 금속의 규화물, 상기 고융점 금속의 질화물, Cu, Al에서 선택되거나 또는 이들을 적층하여 이루어지는 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
  5. 반도체 기판(1), 상기 반도체 기판 상에 형성된 붕소를 포함하는 절연막(4), 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층(5), 상기 패드 베드층을 피복하는 피복막(22,26및27), 상기 붕소를 포함하는 절연막에 형성된 접속 구멍(6), 상기 접속 구멍 내에 매설된 접속 플러그(23) 및 상기 붕소를 포함하는 절연막상에 형성되고 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선(12 및 25)를 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치.
  6. 제5항에 있어서, 상기 배선이 붕소와 반응하여 안정한 생성물을 형성하는 재료로 구성되거나 또는 그 최하층이 상기 재료로 이루어지는 2층 이상의 적층 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
  7. 제5항에 있어서, 상기 패드 베드층이 폴리실리콘, W나 MO 등의 고융점 금속, 상기 고융점 금속의 규화물, 상기 고융점 금속의 질화물, Cu, Al에서 선택되거나 또는 이들을 적층하여 이루어지는 구조를 갖는 것을 특징으로 하는 반도체 집적 회로 장치.
  8. 제5항에 있어서, 상기 패드 베드층 아래에 배치하도록 상기 붕소를 포함하는 절연막에 버퍼층을 매설한 것을 특징으로 하는 반도체 집적 회로 장치.
  9. 반도체 기판 상에 형성된 붕소를 포함하는 절연막을 형성하는 공정, 상기 붕소를 포함하는 절연막에 접속 구멍을 형성하는 공정, 상기 붕소를 포함하는 절연막 전면에 도전막을 형성하고, 이 도전막을 에칭함으로써 상기 붕소를 절연막상 또는 절연막에 설치한 홈 내 및 상기 접속 구멍 내에 각각 패드 베드층과 접속 플러그을 형성하는 공정 및 상기 붕소를 포함하는 절연막상에 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉하는 배선을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
  10. 반도체 기판 상에 형성된 붕소를 포함하는 절연막을 형성하는 공정, 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내에 설치된 패드 베드층을 형성하는 공정, 상기 패드 베드층을 피복하는 피복막을 형성하는 공정, 상기 붕소를 포함하는 절연막에 형성된 접속 구멍을 형성하는 공정, 상기 접속 구멍 내에 접속 플러그를 매설하는 공정 및 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선을 상기 붕소를 포함하는 절연막상에 형성하는 공정을 포함하고 있는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
  11. 제10항에 있어서, 상기 피복막이 접속 플러그를 형성한 후 적어도 일부는 패드 베드 층상에서 제거해 버리는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
  12. 반도체 기판에 도전막을 형성해서 이 도전막을 에칭함으로써 이 반도체 기판의 소자 영역에 배치된 게이트 전극과 버퍼층을 형성하는 공정, 상기 반도체 기판에 붕소를 포함하는 절연막을 형성하여 상기 게이트 전극과 상기 버퍼를 절연막에 매설하는 공정, 상기 붕소를 포함하는 절연막상 또는 이 절연막에 형성한 홈 내 또는 절연막에 관통 구멍을 형성하여 이 관통 구멍내에서 상기 버퍼층과 직접 접하도록 패드 베드층을 형성하는 공정, 상기 붕소를 포함하는 절연막에 접속 구멍을 형성하는 공정, 상기 접속 구멍 내에 접속 플러그를 매설하는 공정 및 상기 패드 베드층상에 배치되어 있는 본딩 패드부을 가지고 상기 접속 플러그와 접촉해 있는 배선을 상기 붕소를 포함하는 절연막상에 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 집적 회로 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920018793A 1991-10-14 1992-10-13 반도체 집적 회로 장치 및 그 제조 방법 KR960005558B1 (ko)

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