JPS6423564A - Space type semiconductor device - Google Patents

Space type semiconductor device

Info

Publication number
JPS6423564A
JPS6423564A JP17983587A JP17983587A JPS6423564A JP S6423564 A JPS6423564 A JP S6423564A JP 17983587 A JP17983587 A JP 17983587A JP 17983587 A JP17983587 A JP 17983587A JP S6423564 A JPS6423564 A JP S6423564A
Authority
JP
Japan
Prior art keywords
layer
silicon layer
wiring
stuck
wiring electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17983587A
Other languages
Japanese (ja)
Inventor
Mitsuo Matsunami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP17983587A priority Critical patent/JPS6423564A/en
Publication of JPS6423564A publication Critical patent/JPS6423564A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To make a device high-density and high-speed, by forming a wiring body on at least one layer of semiconductor single-crystalline layer so that it contains a passive element composed of materials other than a semiconductor. CONSTITUTION:A (n) channel MOSFET 4 is formed on a first silicon layer 1. Wiring electrodes 13-1-13-4 of the lowermost layers are formed with prescribed patterns on a protective insulating film 9 and on a protect insulating film 11 which covers a wiring electrode 10 except the upper surface of the electrode 10. After an interlayer insulating SiO2 film 14-3 and the wiring electrode 13-4 are covered with a polyimide film layer 16, the layer 16 is heated to become semihard and stuck on a second silicon layer 2, so that p-type impurities are diffused into the diffusion layer 6 and the MOSFET 4 becomes a (p) channel. A multilayer interconnection body 12' is formed ranging only up to the wiring electrode 13-3. A through hole 18 is formed, and a protection substrate 20 is stuck on an upper surface of the second silicon layer 2 with wax 21 in between, and a polyimide layer 16 is formed on a rear surface of the layer 2. After a sticking process, the upper surface of the second silicon layer 2 is covered with metallic films 22, 23, and a burial metallic layer 25 is formed by burial processing. Next the upper surface of the wiring electrode 26 is covered with the polyimide film layer 16. A third silicon layer 3 is stuck similarly.
JP17983587A 1987-07-17 1987-07-17 Space type semiconductor device Pending JPS6423564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17983587A JPS6423564A (en) 1987-07-17 1987-07-17 Space type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17983587A JPS6423564A (en) 1987-07-17 1987-07-17 Space type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6423564A true JPS6423564A (en) 1989-01-26

Family

ID=16072729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17983587A Pending JPS6423564A (en) 1987-07-17 1987-07-17 Space type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6423564A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0703623A1 (en) * 1994-09-22 1996-03-27 Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V. Method of fabrication of a vertical integrated circuit structure
JP2001015683A (en) * 1999-04-02 2001-01-19 Interuniv Micro Electronica Centrum Vzw Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same
JP2005012180A (en) * 2003-05-28 2005-01-13 Okutekku:Kk Semiconductor device and its manufacturing method
JP2009188400A (en) * 2008-02-01 2009-08-20 Promos Technologies Inc Semiconductor element with laminate structure, and method of manufacturing the same
JP2011159869A (en) * 2010-02-02 2011-08-18 Nec Corp Laminate structure of semiconductor device and method for manufacturing the same
US8338289B2 (en) 2005-06-30 2012-12-25 Shinko Electric Industries Co., Ltd. Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
US8629059B2 (en) 2008-06-10 2014-01-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit chips having vertically extended through-substrate vias therein

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0703623A1 (en) * 1994-09-22 1996-03-27 Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V. Method of fabrication of a vertical integrated circuit structure
JP2001015683A (en) * 1999-04-02 2001-01-19 Interuniv Micro Electronica Centrum Vzw Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same
JP2005012180A (en) * 2003-05-28 2005-01-13 Okutekku:Kk Semiconductor device and its manufacturing method
US8338289B2 (en) 2005-06-30 2012-12-25 Shinko Electric Industries Co., Ltd. Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
JP2009188400A (en) * 2008-02-01 2009-08-20 Promos Technologies Inc Semiconductor element with laminate structure, and method of manufacturing the same
US8629059B2 (en) 2008-06-10 2014-01-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
US9219035B2 (en) 2008-06-10 2015-12-22 Samsung Electronics Co., Ltd. Integrated circuit chips having vertically extended through-substrate vias therein
JP2011159869A (en) * 2010-02-02 2011-08-18 Nec Corp Laminate structure of semiconductor device and method for manufacturing the same

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