JPS6489539A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6489539A
JPS6489539A JP24709687A JP24709687A JPS6489539A JP S6489539 A JPS6489539 A JP S6489539A JP 24709687 A JP24709687 A JP 24709687A JP 24709687 A JP24709687 A JP 24709687A JP S6489539 A JPS6489539 A JP S6489539A
Authority
JP
Japan
Prior art keywords
layer
forming
wiring layer
wiring
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24709687A
Other languages
Japanese (ja)
Other versions
JP2551030B2 (en
Inventor
Shinichi Ito
Masataka Shingu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62247096A priority Critical patent/JP2551030B2/en
Publication of JPS6489539A publication Critical patent/JPS6489539A/en
Application granted granted Critical
Publication of JP2551030B2 publication Critical patent/JP2551030B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent removal of an insulating layer located at a stepped part by forming second and third wiring layers on a first wiring layer, and by getting the second wiring layer to be coated at the time of forming an opening part. CONSTITUTION:A gate oxide film 3 is formed on a silicon substrate 1 after forming a field oxide film 2. Then after forming a wiring layer 4 consisting of a polycrystalline silicon layer on the gate oxide film 3 and patterning it, impurity regions 5, 6 are formed on the silicon substrate 1. Then when forming an insulating layer 7 consisting of an SiO2 layer or the like over the entire surface and coating the wiring layer 4, stepped parts 7a, 7a are likewise formed on the insulating layer 7. An opening part 9 is formed to expose the impurity region 5 after forming a wiring layer 8 consisting entirely of a polycrystalline silicon. Then a wiring layer 10 is formed using the polycrystalline silicon layer after light etching or ammonia hydrolytic treatment. Both wiring layers 8 and 10 are patterned as predetermined. According to the constitution, the stepped parts 7a, 7a on the interlayer insulating layer 7 are not to be removed by etching, whereby interlayer pressure resistance can be improved.
JP62247096A 1987-09-30 1987-09-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2551030B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62247096A JP2551030B2 (en) 1987-09-30 1987-09-30 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247096A JP2551030B2 (en) 1987-09-30 1987-09-30 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6489539A true JPS6489539A (en) 1989-04-04
JP2551030B2 JP2551030B2 (en) 1996-11-06

Family

ID=17158369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247096A Expired - Fee Related JP2551030B2 (en) 1987-09-30 1987-09-30 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2551030B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5900554A (en) * 1995-07-28 1999-05-04 Nippendenso Co., Ltd. Pressure sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5900554A (en) * 1995-07-28 1999-05-04 Nippendenso Co., Ltd. Pressure sensor

Also Published As

Publication number Publication date
JP2551030B2 (en) 1996-11-06

Similar Documents

Publication Publication Date Title
JPS55163860A (en) Manufacture of semiconductor device
JPS56134757A (en) Complementary type mos semiconductor device and its manufacture
JPS6433969A (en) Manufacture of semiconductor device
JPS5599722A (en) Preparation of semiconductor device
GB1453270A (en) Field effect devices
JPS5599744A (en) Manufacture of semiconductor device
EP0081226A3 (en) Method of making semiconductor device
JPS6410222A (en) Substrate for thin film passive element
JPS6489539A (en) Manufacture of semiconductor device
JPS6441240A (en) Semiconductor integrated circuit device
JPS5764927A (en) Manufacture of semiconductor device
JPS57204146A (en) Manufacture of semiconductor device
JPS5740967A (en) Integrated circuit device
JPS6425551A (en) Semiconductor device
JPS5461490A (en) Multi-layer wiring forming method in semiconductor device
JPS5459889A (en) Semiconductor device
JPS577153A (en) Preparation of semiconductor device
JPS551157A (en) Method of fabricating semiconductor device
JPS5797643A (en) Manufacture of semiconductor device
JPS5642373A (en) Manufacture of semiconductor device
JPS5687346A (en) Manufacture of semiconductor device
JPS5575243A (en) Method of fabricating mis semiconductor device having two-layer polycrystalline silicon wired layer
JPS5656675A (en) Semiconductor device on insulated substrate
JPS56142641A (en) Semiconductor device
JPS54111783A (en) Manufacture for semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees