KR920017184A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

Info

Publication number
KR920017184A
KR920017184A KR1019920002246A KR920002246A KR920017184A KR 920017184 A KR920017184 A KR 920017184A KR 1019920002246 A KR1019920002246 A KR 1019920002246A KR 920002246 A KR920002246 A KR 920002246A KR 920017184 A KR920017184 A KR 920017184A
Authority
KR
South Korea
Prior art keywords
barrier layer
oxide film
forming
manufacturing
semiconductor device
Prior art date
Application number
KR1019920002246A
Other languages
English (en)
Other versions
KR960005038B1 (ko
Inventor
히데오 다카기
아키히로 요시다
Original Assignee
세키자와 스토무
후지쓰 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세키자와 스토무, 후지쓰 가부시기가이샤 filed Critical 세키자와 스토무
Publication of KR920017184A publication Critical patent/KR920017184A/ko
Application granted granted Critical
Publication of KR960005038B1 publication Critical patent/KR960005038B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/147Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제4도는 본 발명의 일시시예에 따른 제조방법의 단계를 설명하기위한 단면도, 제5도는 본 발명에서 사용되는 열처리 피네이스의 구조의 일예를 나타내는 단면도.

Claims (6)

  1. 반도체장치의 제조방법에 있어서, 최소한 하나의 금속으로 이루어진 장벽층을 반도체 기판의 표면상에 형성하고 그 표면이 산화될때 그 표면상에 산화막이 형성될수 있게 하는 단계와, 대기나 대기와 거의 동일한 성분을 갖는 분위기에서 상기 장벽층을 가열함으로써 상기 장벽층의 표면상에 터널 효과에 의해 전류를 통전시킬수 있을 정도의 두께를 가진 산화막을 형성하는 단계와, 알루미늄, 알루미늄 합금, 텅스텐, 금 및 구리중 어느 하나로 이루어진 도전층을 상기 산화막이 위에 형성된 상기 장벽층 상에 용착하는 단계와; 상기 도전층, 상기 산화막 및 상기 장벽층을 연속적으로 에칭함으로써 배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
  2. 제1항에 있어서, 상기 장벽층은 고융점 금속질화물을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
  3. 제1항에 있어서, 상기 장벽층은 금속 규소막을 포함한 것을 특징으로 하는 반도체 장치 제조방법.
  4. 반도체장치의 제조방법에 있어서, 최소한 하나의 금속으로 이루어진 장벽층을 반도체 기판의 표면상에 형성하고 그 표면이 산화될때 그 표면상에 산화막이 형성될 수 있게 하는 단계와, 산화성 화학물질 내에 상기 장벽층을 침전시킴으로써 상기 장벽층의 표면상에 터널효과에 의해 전류를 통전시킬수 있을 정도의 두께를 가진 산화막을 형성하는 단계와, 알루미늄, 알루미늄 합금, 텅스텐, 금 및 구리중 어느 하나로 이루어진 도전층을 상기 산화막이 위에 형성된 상기 장벽측 상에 용착하는 단계와; 상기 도전층, 상기 산화막 및 상기 장벽층을 연속적으로 에칭함으로써 배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
  5. 제4항에 있어서, 상기 장벽층은 고융점 금속질화물을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
  6. 제4항에 있어서, 상기 장벽층은 금속 규소막을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920002246A 1991-02-14 1992-02-14 반도체 장치의 제조방법 KR960005038B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3020605A JPH04259242A (ja) 1991-02-14 1991-02-14 半導体装置の製造方法
JP91-020605 1991-02-14
JP91-20605 1991-02-14

Publications (2)

Publication Number Publication Date
KR920017184A true KR920017184A (ko) 1992-09-26
KR960005038B1 KR960005038B1 (ko) 1996-04-18

Family

ID=12031901

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920002246A KR960005038B1 (ko) 1991-02-14 1992-02-14 반도체 장치의 제조방법

Country Status (4)

Country Link
US (1) US5236869A (ko)
EP (1) EP0499249A3 (ko)
JP (1) JPH04259242A (ko)
KR (1) KR960005038B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472259B1 (ko) * 2001-03-28 2005-03-08 샤프 가부시키가이샤 접착특성 및 트렌치 충전특성을 향상시키는 구리 증착전의 배리어금속 표면처리방법

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950009934B1 (ko) * 1992-09-07 1995-09-01 삼성전자주식회사 반도체 장치의 배선층 형성방법
US5378660A (en) * 1993-02-12 1995-01-03 Applied Materials, Inc. Barrier layers and aluminum contacts
JP3201061B2 (ja) * 1993-03-05 2001-08-20 ソニー株式会社 配線構造の製造方法
US5506449A (en) * 1993-03-24 1996-04-09 Kawasaki Steel Corporation Interconnection structure for semiconductor integrated circuit and manufacture of the same
GB2285337B (en) * 1993-12-28 1997-12-17 Fujitsu Ltd Manufacture of semiconductor device with aluminium wiring
DE19515564B4 (de) 1994-04-28 2008-07-03 Denso Corp., Kariya Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben
US5514908A (en) * 1994-04-29 1996-05-07 Sgs-Thomson Microelectronics, Inc. Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
TW319891B (en) * 1996-02-02 1997-11-11 Taiwan Semiconductor Mfg Method for improved aluminium-copper deposition and robust via contact resistance
US5693561A (en) * 1996-05-14 1997-12-02 Lucent Technologies Inc. Method of integrated circuit fabrication including a step of depositing tungsten
US5913144A (en) * 1996-09-20 1999-06-15 Sharp Microelectronics Technology, Inc. Oxidized diffusion barrier surface for the adherence of copper and method for same
US5918150A (en) * 1996-10-11 1999-06-29 Sharp Microelectronics Technology, Inc. Method for a chemical vapor deposition of copper on an ion prepared conductive surface
JP3974284B2 (ja) * 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
US6724088B1 (en) * 1999-04-20 2004-04-20 International Business Machines Corporation Quantum conductive barrier for contact to shallow diffusion region
JP2001060590A (ja) 1999-08-20 2001-03-06 Denso Corp 半導体装置の電気配線及びその製造方法
US6433429B1 (en) * 1999-09-01 2002-08-13 International Business Machines Corporation Copper conductive line with redundant liner and method of making
JP3648480B2 (ja) * 2001-12-26 2005-05-18 株式会社東芝 半導体装置およびその製造方法
KR100919378B1 (ko) * 2002-10-28 2009-09-25 매그나칩 반도체 유한회사 반도체 소자의 금속 배선 및 이의 형성 방법
WO2007131343A1 (en) * 2006-05-15 2007-11-22 Arise Technologies Corporation Low-temperature doping processes for silicon wafer devices
JP5057113B2 (ja) * 2009-11-17 2012-10-24 セイコーエプソン株式会社 半導体装置および電子部品並びにそれらの製造方法
US9786762B2 (en) 2012-08-29 2017-10-10 Longitude Semiconductor S.A.R.L. Gate electrode of a semiconductor device, and method for producing same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
US4200474A (en) * 1978-11-20 1980-04-29 Texas Instruments Incorporated Method of depositing titanium dioxide (rutile) as a gate dielectric for MIS device fabrication
JPS5948647A (ja) * 1982-09-13 1984-03-19 Mitsubishi Electric Corp 感湿材料の製造方法
JPS61110449A (ja) * 1984-11-05 1986-05-28 Hitachi Ltd 半導体装置の製造方法
US4839010A (en) * 1985-08-30 1989-06-13 Texas Instruments Incorporated Forming an antireflective coating for VLSI metallization
JPS62113421A (ja) * 1985-11-13 1987-05-25 Toshiba Corp 半導体装置の製造方法
NL9000602A (nl) * 1990-03-16 1991-10-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met geheugenelementen vormende condensatoren met een ferroelectrisch dielectricum.
US5175126A (en) * 1990-12-27 1992-12-29 Intel Corporation Process of making titanium nitride barrier layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472259B1 (ko) * 2001-03-28 2005-03-08 샤프 가부시키가이샤 접착특성 및 트렌치 충전특성을 향상시키는 구리 증착전의 배리어금속 표면처리방법

Also Published As

Publication number Publication date
KR960005038B1 (ko) 1996-04-18
EP0499249A3 (en) 1993-02-24
EP0499249A2 (en) 1992-08-19
JPH04259242A (ja) 1992-09-14
US5236869A (en) 1993-08-17

Similar Documents

Publication Publication Date Title
KR920017184A (ko) 반도체 장치의 제조방법
KR890007386A (ko) 반도체 장치 및 그 제조방법
KR920020620A (ko) 반도체 집적회로장치의 배선접속구조 및 그 제조방법
KR890001178A (ko) 초전도재의 배선을 가지는 반도체장치
KR930009050A (ko) 반도체 집적 회로 장치 및 그 제조 방법
KR870007565A (ko) 반도체장치 및 그 제조방법
KR950034682A (ko) 반도체 소자의 금속배선 제조방법
KR960026643A (ko) 반도체장치의 배선 제조방법
KR920020618A (ko) 반도체 장치의 배선 접속 구조 및 그 제조방법
KR900005602A (ko) 반도체장치 및 그 제조방법
KR930003256A (ko) 반도체 집적 회로에 금속화 배선층을 형성하는 방법
KR870004504A (ko) 반도체 장치 및 그 제조방법
KR960027004A (ko) 반도체 장치의 측면콘택 형성방법
KR890012361A (ko) 반도체 소자 제조방법
KR930020590A (ko) 알루미늄을 주성분으로 하는 금속박막의 에칭방법 및 박막트랜지스터의 제조방법
KR930024103A (ko) 반도체 장치의 제조방법
KR930011461B1 (ko) 반도체 집접회로의 서브미크론 전극배선 형성방법
KR970063500A (ko) 반도체소자의 금속배선 형성방법
KR890004874B1 (ko) 반도체 장치의 폴리사이드 구조
KR100222124B1 (ko) 반도체 소자의 금속 배선 형성방법
KR940010179A (ko) 반도체장치의 층간절연막 평탄화방법
KR930006888A (ko) 금속 배선막 형성방법
KR19990004661A (ko) 반도체 소자 및 그의 제조방법
KR930011183A (ko) 텅스텐 금속배선의 산화방지를 위한 질화막형성방법
KR19990004408A (ko) 반도체 소자의 다층 금속 배선 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080411

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee