KR920017184A - 반도체 장치의 제조방법 - Google Patents
반도체 장치의 제조방법 Download PDFInfo
- Publication number
- KR920017184A KR920017184A KR1019920002246A KR920002246A KR920017184A KR 920017184 A KR920017184 A KR 920017184A KR 1019920002246 A KR1019920002246 A KR 1019920002246A KR 920002246 A KR920002246 A KR 920002246A KR 920017184 A KR920017184 A KR 920017184A
- Authority
- KR
- South Korea
- Prior art keywords
- barrier layer
- oxide film
- forming
- manufacturing
- semiconductor device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 13
- 229910052751 metal Inorganic materials 0.000 claims 6
- 239000002184 metal Substances 0.000 claims 6
- 238000000034 method Methods 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 3
- 229910000838 Al alloy Inorganic materials 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 238000002844 melting Methods 0.000 claims 2
- 230000008018 melting Effects 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- 239000010937 tungsten Substances 0.000 claims 2
- 235000005205 Pinus Nutrition 0.000 description 1
- 241000218602 Pinus <genus> Species 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제4도는 본 발명의 일시시예에 따른 제조방법의 단계를 설명하기위한 단면도, 제5도는 본 발명에서 사용되는 열처리 피네이스의 구조의 일예를 나타내는 단면도.
Claims (6)
- 반도체장치의 제조방법에 있어서, 최소한 하나의 금속으로 이루어진 장벽층을 반도체 기판의 표면상에 형성하고 그 표면이 산화될때 그 표면상에 산화막이 형성될수 있게 하는 단계와, 대기나 대기와 거의 동일한 성분을 갖는 분위기에서 상기 장벽층을 가열함으로써 상기 장벽층의 표면상에 터널 효과에 의해 전류를 통전시킬수 있을 정도의 두께를 가진 산화막을 형성하는 단계와, 알루미늄, 알루미늄 합금, 텅스텐, 금 및 구리중 어느 하나로 이루어진 도전층을 상기 산화막이 위에 형성된 상기 장벽층 상에 용착하는 단계와; 상기 도전층, 상기 산화막 및 상기 장벽층을 연속적으로 에칭함으로써 배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
- 제1항에 있어서, 상기 장벽층은 고융점 금속질화물을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
- 제1항에 있어서, 상기 장벽층은 금속 규소막을 포함한 것을 특징으로 하는 반도체 장치 제조방법.
- 반도체장치의 제조방법에 있어서, 최소한 하나의 금속으로 이루어진 장벽층을 반도체 기판의 표면상에 형성하고 그 표면이 산화될때 그 표면상에 산화막이 형성될 수 있게 하는 단계와, 산화성 화학물질 내에 상기 장벽층을 침전시킴으로써 상기 장벽층의 표면상에 터널효과에 의해 전류를 통전시킬수 있을 정도의 두께를 가진 산화막을 형성하는 단계와, 알루미늄, 알루미늄 합금, 텅스텐, 금 및 구리중 어느 하나로 이루어진 도전층을 상기 산화막이 위에 형성된 상기 장벽측 상에 용착하는 단계와; 상기 도전층, 상기 산화막 및 상기 장벽층을 연속적으로 에칭함으로써 배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
- 제4항에 있어서, 상기 장벽층은 고융점 금속질화물을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.
- 제4항에 있어서, 상기 장벽층은 금속 규소막을 포함하는 것을 특징으로 하는 반도체 장치 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3020605A JPH04259242A (ja) | 1991-02-14 | 1991-02-14 | 半導体装置の製造方法 |
JP91-020605 | 1991-02-14 | ||
JP91-20605 | 1991-02-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920017184A true KR920017184A (ko) | 1992-09-26 |
KR960005038B1 KR960005038B1 (ko) | 1996-04-18 |
Family
ID=12031901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920002246A KR960005038B1 (ko) | 1991-02-14 | 1992-02-14 | 반도체 장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5236869A (ko) |
EP (1) | EP0499249A3 (ko) |
JP (1) | JPH04259242A (ko) |
KR (1) | KR960005038B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100472259B1 (ko) * | 2001-03-28 | 2005-03-08 | 샤프 가부시키가이샤 | 접착특성 및 트렌치 충전특성을 향상시키는 구리 증착전의 배리어금속 표면처리방법 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950009934B1 (ko) * | 1992-09-07 | 1995-09-01 | 삼성전자주식회사 | 반도체 장치의 배선층 형성방법 |
US5378660A (en) * | 1993-02-12 | 1995-01-03 | Applied Materials, Inc. | Barrier layers and aluminum contacts |
JP3201061B2 (ja) * | 1993-03-05 | 2001-08-20 | ソニー株式会社 | 配線構造の製造方法 |
US5506449A (en) * | 1993-03-24 | 1996-04-09 | Kawasaki Steel Corporation | Interconnection structure for semiconductor integrated circuit and manufacture of the same |
GB2285337B (en) * | 1993-12-28 | 1997-12-17 | Fujitsu Ltd | Manufacture of semiconductor device with aluminium wiring |
DE19515564B4 (de) | 1994-04-28 | 2008-07-03 | Denso Corp., Kariya | Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben |
US5514908A (en) * | 1994-04-29 | 1996-05-07 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries |
TW319891B (en) * | 1996-02-02 | 1997-11-11 | Taiwan Semiconductor Mfg | Method for improved aluminium-copper deposition and robust via contact resistance |
US5693561A (en) * | 1996-05-14 | 1997-12-02 | Lucent Technologies Inc. | Method of integrated circuit fabrication including a step of depositing tungsten |
US5913144A (en) * | 1996-09-20 | 1999-06-15 | Sharp Microelectronics Technology, Inc. | Oxidized diffusion barrier surface for the adherence of copper and method for same |
US5918150A (en) * | 1996-10-11 | 1999-06-29 | Sharp Microelectronics Technology, Inc. | Method for a chemical vapor deposition of copper on an ion prepared conductive surface |
JP3974284B2 (ja) * | 1999-03-18 | 2007-09-12 | 株式会社東芝 | 半導体装置の製造方法 |
US6724088B1 (en) * | 1999-04-20 | 2004-04-20 | International Business Machines Corporation | Quantum conductive barrier for contact to shallow diffusion region |
JP2001060590A (ja) | 1999-08-20 | 2001-03-06 | Denso Corp | 半導体装置の電気配線及びその製造方法 |
US6433429B1 (en) * | 1999-09-01 | 2002-08-13 | International Business Machines Corporation | Copper conductive line with redundant liner and method of making |
JP3648480B2 (ja) * | 2001-12-26 | 2005-05-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR100919378B1 (ko) * | 2002-10-28 | 2009-09-25 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선 및 이의 형성 방법 |
WO2007131343A1 (en) * | 2006-05-15 | 2007-11-22 | Arise Technologies Corporation | Low-temperature doping processes for silicon wafer devices |
JP5057113B2 (ja) * | 2009-11-17 | 2012-10-24 | セイコーエプソン株式会社 | 半導体装置および電子部品並びにそれらの製造方法 |
US9786762B2 (en) | 2012-08-29 | 2017-10-10 | Longitude Semiconductor S.A.R.L. | Gate electrode of a semiconductor device, and method for producing same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4307132A (en) * | 1977-12-27 | 1981-12-22 | International Business Machines Corp. | Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer |
US4200474A (en) * | 1978-11-20 | 1980-04-29 | Texas Instruments Incorporated | Method of depositing titanium dioxide (rutile) as a gate dielectric for MIS device fabrication |
JPS5948647A (ja) * | 1982-09-13 | 1984-03-19 | Mitsubishi Electric Corp | 感湿材料の製造方法 |
JPS61110449A (ja) * | 1984-11-05 | 1986-05-28 | Hitachi Ltd | 半導体装置の製造方法 |
US4839010A (en) * | 1985-08-30 | 1989-06-13 | Texas Instruments Incorporated | Forming an antireflective coating for VLSI metallization |
JPS62113421A (ja) * | 1985-11-13 | 1987-05-25 | Toshiba Corp | 半導体装置の製造方法 |
NL9000602A (nl) * | 1990-03-16 | 1991-10-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met geheugenelementen vormende condensatoren met een ferroelectrisch dielectricum. |
US5175126A (en) * | 1990-12-27 | 1992-12-29 | Intel Corporation | Process of making titanium nitride barrier layer |
-
1991
- 1991-02-14 JP JP3020605A patent/JPH04259242A/ja active Pending
-
1992
- 1992-02-10 US US07/833,003 patent/US5236869A/en not_active Expired - Lifetime
- 1992-02-13 EP EP19920102410 patent/EP0499249A3/en not_active Withdrawn
- 1992-02-14 KR KR1019920002246A patent/KR960005038B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100472259B1 (ko) * | 2001-03-28 | 2005-03-08 | 샤프 가부시키가이샤 | 접착특성 및 트렌치 충전특성을 향상시키는 구리 증착전의 배리어금속 표면처리방법 |
Also Published As
Publication number | Publication date |
---|---|
KR960005038B1 (ko) | 1996-04-18 |
EP0499249A3 (en) | 1993-02-24 |
EP0499249A2 (en) | 1992-08-19 |
JPH04259242A (ja) | 1992-09-14 |
US5236869A (en) | 1993-08-17 |
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