KR890012361A - 반도체 소자 제조방법 - Google Patents

반도체 소자 제조방법 Download PDF

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Publication number
KR890012361A
KR890012361A KR1019890000785A KR890000785A KR890012361A KR 890012361 A KR890012361 A KR 890012361A KR 1019890000785 A KR1019890000785 A KR 1019890000785A KR 890000785 A KR890000785 A KR 890000785A KR 890012361 A KR890012361 A KR 890012361A
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South Korea
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layer
conductor track
semiconductor
track
semiconductor device
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KR1019890000785A
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KR0158441B1 (ko
Inventor
아드리아누스 마리아 볼테르스 로베르투스
기예스베르투스 마티아스 욘케르스 알렉산더
Original Assignee
이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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Publication of KR890012361A publication Critical patent/KR890012361A/ko
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Publication of KR0158441B1 publication Critical patent/KR0158441B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/015—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

내용 없음.

Description

반도체 소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1내지 3도는 본 발명에 따른 방법에 의해서 형성된 반도체 소자의 제조에 대한 몇몇 연속 단계를 개략적으로 절단면으로 도시한 도면.

Claims (9)

  1. 반도체 영역과 이 영역을 둘러싸는 필드 산화물 영역에 인접해 있는 표면을 갖고 있는 반도체 몸체를 포함하는 반도체 소자를 제조하는 방법에서, 이 반도체 몸체 표면에는 금속층에 제공되고, 이 층에서 전도체 트랙이 형성되고, 그후 실리콘 산화물의 절연층이 상기 표면상에 반도체 트랙 위에 배치되는 이러한 반도체 소자 제조 방법에 있어서, 실리콘 산화물의 층이 전도체 트랙 위에 제공되기 전에 이 트랙에는 산화-방지 재료의 상층이 제공되는 것을 특징으로 하는 반도체 소자 제조방법.
  2. 제1항에 있어서, 반도체 트랙에는 산화-방지 상층으로 무정형의 상층이 제공되는 것을 특징으로 하는 반도체 소자 제조 방법.
  3. 제2항에 있어서, 전도체 트랙에는 적어도 3nm두께를 갖는 무정형 실리콘의 상층이 제공되는 것을 특징으로 하는 반도체 소자 방법.
  4. 제1,2 또는 3항에 있어서, 전도체 트랙에는 상층을 산화-방치 재료의 표면층상에 배치된 금속층상에 배치시키고 그후에 두 평행층을 전도체 트랙에 대응하는 동일 패턴으로 에칭 하므로써 상층이 배치되는 것을 특징으로 하는 반도체 소자 제조방법.
  5. 제4항에 있어서, 산화-방지 재료의 층이 먼저 상기 패턴으로 에치되고, 그후에 언더라이닝 금속층에 산화 방지 재료의 층내에 마스킹을 만드는 동안 패턴으로 에치되는 것을 특징으로 하는 반도체 소자 제조방법.
  6. 제5항에 있어서, 전도체 트랙은 텅스텐과 티타늄의 혼합물층에 형성되고, 그 위에 니트로겐이 첨가되는 것을 특징으로 하는 반도체 소자 제조방법.
  7. 제6항에 있어서, 니트로겐의 10내지 30at.%는 텅스텐과 티타늄을 1 : 4의 비율로 함유하는 혼합물에 첨가되는 것을 특징으로 하는 반도체 소자 제조방법.
  8. 선행항중 임의 한 항에 있어서, 전도체 트랙이 형성되는 금속층이 제공되기 전에, 반도체 영역에서 적어도 국부적으로 금속 실리사이드의 상층이 제공되는 것을 특징으로 하는 반도체 소자 제조방법.
  9. 제8항에 있어서, 금속 실리사이드의 상층은 니트로겐-함유 대기중에서 5내지 20초 동안 600과 700℃사이의 온도에서 가열 처리 하므로써 형성되는 것을 특징으로 하는 반도체 소자 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890000785A 1988-01-29 1989-01-26 반도체 소자 제조 방법 KR0158441B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8800220 1988-01-29
NL8800220A NL8800220A (nl) 1988-01-29 1988-01-29 Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij een metalen geleiderspoor op een oppervlak van een halfgeleiderlichaam wordt gebracht.

Publications (2)

Publication Number Publication Date
KR890012361A true KR890012361A (ko) 1989-08-26
KR0158441B1 KR0158441B1 (ko) 1999-02-01

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ID=19851678

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890000785A KR0158441B1 (ko) 1988-01-29 1989-01-26 반도체 소자 제조 방법

Country Status (6)

Country Link
US (1) US5366928A (ko)
EP (1) EP0326218A1 (ko)
JP (1) JP2664757B2 (ko)
KR (1) KR0158441B1 (ko)
CN (1) CN1016297B (ko)
NL (1) NL8800220A (ko)

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US5500557A (en) * 1992-04-30 1996-03-19 Sgs-Thomson Microelectronics, Inc. Structure and method for fabricating integrated circuits
US5444302A (en) 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
US5621235A (en) * 1993-01-12 1997-04-15 Texas Instruments Incorporated TiSi2 /TiN clad interconnect technology
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JP2001036080A (ja) * 1999-07-26 2001-02-09 Mitsubishi Electric Corp 半導体装置及びその製造方法

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Also Published As

Publication number Publication date
NL8800220A (nl) 1989-08-16
JPH02205343A (ja) 1990-08-15
US5366928A (en) 1994-11-22
CN1034826A (zh) 1989-08-16
KR0158441B1 (ko) 1999-02-01
CN1016297B (zh) 1992-04-15
EP0326218A1 (en) 1989-08-02
JP2664757B2 (ja) 1997-10-22

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