KR940006246A - 반도체 디바이스용 유전체 구조 및 그 제조방법 - Google Patents

반도체 디바이스용 유전체 구조 및 그 제조방법 Download PDF

Info

Publication number
KR940006246A
KR940006246A KR1019930012268A KR930012268A KR940006246A KR 940006246 A KR940006246 A KR 940006246A KR 1019930012268 A KR1019930012268 A KR 1019930012268A KR 930012268 A KR930012268 A KR 930012268A KR 940006246 A KR940006246 A KR 940006246A
Authority
KR
South Korea
Prior art keywords
dielectric layer
primary
forming
primary dielectric
dielectric
Prior art date
Application number
KR1019930012268A
Other languages
English (en)
Other versions
KR100267440B1 (ko
Inventor
윤 유식
피. 코박스 로날드
이. 토마스 미카엘
Original Assignee
존 엠. 클락 3세
내쇼날 세미컨덕터 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 존 엠. 클락 3세, 내쇼날 세미컨덕터 코포레이션 filed Critical 존 엠. 클락 3세
Publication of KR940006246A publication Critical patent/KR940006246A/ko
Application granted granted Critical
Publication of KR100267440B1 publication Critical patent/KR100267440B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

기판상에 제공된 유전체 구조는, 상기 기판상에 형성된 1차 유전체 층으로서, 1차 유전체가 탄탈륨 펜톡사이드와 같이 높은 유전 상수를 갖는 금속 산화물인 1차 유전체 층, 및 상기 1차 유전체 층상에 형성된 실리콘 옥사이드 또는 실리콘 니트라이드와 같은 2차 유전체 층을 포함한다. 한 실시예에서, 다층 구조는 2차 유전체 층상에 배치된 제2의 1차 유전체층, 및 제2의 1차 유전체 층상에 배치된 제2의 2차 유전체 층을 포함하는데, 각각의 1차 유전체 층은 제공된 인가 전계에 대하여 적은 누설 전류를 특징으로 하는 제1의 결정질 상태를 이룬다. 기판상에 유전체 구조를 형성하는 방법은, 높은 유전 상수를 갖는 금속 산화물인 1차 유전체 층을 형성하는 단계, 상기 1차 유전체 층상에 2차 유전체 층을 형성하는 단계, 및 상기 1차 유전체 층을 어닐링하는 단계를 포함한다.

Description

반도체 디바이스용 유전체 구조 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 방법의 제1단계전에 형성된 기판의 단면도,
제2도는 제1도와 유사하며, 제1의 2차 유전체층을 제공하는 단계 후에 형성된 단면도,
제3도는 제2도와 유사하며, 제1의 유전체층을 제공하는 단계 후에 형성된 단면도,
제4도는 제3도와 유사하며, 제2의 2차 유전체층을 제공하는 단계 후에 형성된 단면도,
제5도는 제4도와 유사하며, 재산화 단계후에 형성된 단면도,
제6도는 제5도와 유사하며, 전극을 제공하는 단계후에 형성된 단면도,
제7도는 본 발명의 변형 실시예에 따른 방법의 공정 단계의 단면도,
제8도는 제7도와 유사하며, 2차 유전체층을 형성하는 단계후에 형성된 단면도.

Claims (1)

  1. (a) 반도체 기판상에 형성되어 있는 제1의 1차 유전체 층으로서, 1차 유전체가 높은 유전 상수를 갖는 금속 산화물인 제1의 1차 유전체 층, 및 (b) 상기 제1의 유전체 층상에 제공되어 있는 제1의 2차 유전체 층을 포함하는, 반도체 기판상에 제공된 유전체 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930012268A 1992-07-02 1993-07-01 반도체 디바이스용 유전체 구조 및 그 제조방법 KR100267440B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US90791592A 1992-07-02 1992-07-02
US7/907,915 1992-07-02
US92-07/907,915 1992-07-02

Publications (2)

Publication Number Publication Date
KR940006246A true KR940006246A (ko) 1994-03-23
KR100267440B1 KR100267440B1 (ko) 2000-10-16

Family

ID=25424849

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930012268A KR100267440B1 (ko) 1992-07-02 1993-07-01 반도체 디바이스용 유전체 구조 및 그 제조방법

Country Status (3)

Country Link
US (1) US5688724A (ko)
JP (1) JPH0677402A (ko)
KR (1) KR100267440B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411735B1 (ko) * 2001-07-09 2003-12-18 일성기계공업 주식회사 건조기의 열풍 분사노즐 조립구조

Families Citing this family (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0851103A (ja) * 1994-08-08 1996-02-20 Fuji Electric Co Ltd 薄膜の生成方法
KR0183732B1 (ko) * 1995-09-01 1999-03-20 김광호 반도체 장치의 캐패시터 제작방법
US6555394B2 (en) 1995-11-28 2003-04-29 Samsung Electronics Co., Ltd. Methods of fabricating capacitors including Ta2O5 layers in a chamber including changing a Ta2O5 layer to heater separation or chamber pressure
KR0165484B1 (ko) 1995-11-28 1999-02-01 김광호 탄탈륨산화막 증착 형성방법 및 그 장치
JP3105788B2 (ja) * 1996-07-15 2000-11-06 日本電気株式会社 半導体装置の製造方法
US6251720B1 (en) * 1996-09-27 2001-06-26 Randhir P. S. Thakur High pressure reoxidation/anneal of high dielectric constant materials
JP5731121B2 (ja) * 1996-12-23 2015-06-10 エルエスアイ コーポレーション 集積回路
US5960302A (en) * 1996-12-31 1999-09-28 Lucent Technologies, Inc. Method of making a dielectric for an integrated circuit
US5910880A (en) 1997-08-20 1999-06-08 Micron Technology, Inc. Semiconductor circuit components and capacitors
US6278166B1 (en) * 1997-12-12 2001-08-21 Advanced Micro Devices, Inc. Use of nitric oxide surface anneal to provide reaction barrier for deposition of tantalum pentoxide
US6258675B1 (en) * 1997-12-18 2001-07-10 Advanced Micro Devices, Inc. High K gate electrode
US6191443B1 (en) 1998-02-28 2001-02-20 Micron Technology, Inc. Capacitors, methods of forming capacitors, and DRAM memory cells
US6162744A (en) * 1998-02-28 2000-12-19 Micron Technology, Inc. Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers
US6111285A (en) 1998-03-17 2000-08-29 Micron Technology, Inc. Boride electrodes and barriers for cell dielectrics
US6730559B2 (en) 1998-04-10 2004-05-04 Micron Technology, Inc. Capacitors and methods of forming capacitors
US6156638A (en) * 1998-04-10 2000-12-05 Micron Technology, Inc. Integrated circuitry and method of restricting diffusion from one material to another
US6284663B1 (en) * 1998-04-15 2001-09-04 Agere Systems Guardian Corp. Method for making field effect devices and capacitors with thin film dielectrics and resulting devices
US6001741A (en) * 1998-04-15 1999-12-14 Lucent Technologies Inc. Method for making field effect devices and capacitors with improved thin film dielectrics and resulting devices
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US6255186B1 (en) 1998-05-21 2001-07-03 Micron Technology, Inc. Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom
US6727148B1 (en) * 1998-06-30 2004-04-27 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator
US6162738A (en) * 1998-09-01 2000-12-19 Micron Technology, Inc. Cleaning compositions for high dielectric structures and methods of using same
SE513116C2 (sv) * 1998-11-13 2000-07-10 Ericsson Telefon Ab L M Polykiselresistor och sätt att framställa sådan
JP3189813B2 (ja) * 1998-11-30 2001-07-16 日本電気株式会社 半導体装置の製造方法
KR100455737B1 (ko) * 1998-12-30 2005-04-19 주식회사 하이닉스반도체 반도체소자의게이트산화막형성방법
US6750500B1 (en) 1999-01-05 2004-06-15 Micron Technology, Inc. Capacitor electrode for integrating high K materials
KR100304699B1 (ko) * 1999-01-05 2001-09-26 윤종용 탄탈륨 산화막을 갖춘 커패시터 제조방법
US6235594B1 (en) 1999-01-13 2001-05-22 Agere Systems Guardian Corp. Methods of fabricating an integrated circuit device with composite oxide dielectric
US20010013616A1 (en) * 1999-01-13 2001-08-16 Sailesh Mansinh Merchant Integrated circuit device with composite oxide dielectric
JP3417866B2 (ja) * 1999-03-11 2003-06-16 株式会社東芝 半導体装置およびその製造方法
US6445023B1 (en) 1999-03-16 2002-09-03 Micron Technology, Inc. Mixed metal nitride and boride barrier layers
US6303047B1 (en) 1999-03-22 2001-10-16 Lsi Logic Corporation Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same
US6524974B1 (en) 1999-03-22 2003-02-25 Lsi Logic Corporation Formation of improved low dielectric constant carbon-containing silicon oxide dielectric material by reaction of carbon-containing silane with oxidizing agent in the presence of one or more reaction retardants
US6204192B1 (en) 1999-03-29 2001-03-20 Lsi Logic Corporation Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
US6046081A (en) * 1999-06-10 2000-04-04 United Microelectronics Corp. Method for forming dielectric layer of capacitor
US6232658B1 (en) * 1999-06-30 2001-05-15 Lsi Logic Corporation Process to prevent stress cracking of dielectric films on semiconductor wafers
KR100624927B1 (ko) * 1999-08-09 2006-09-19 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
US6391795B1 (en) 1999-10-22 2002-05-21 Lsi Logic Corporation Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
US6423628B1 (en) 1999-10-22 2002-07-23 Lsi Logic Corporation Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
US6756674B1 (en) 1999-10-22 2004-06-29 Lsi Logic Corporation Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
US6316354B1 (en) 1999-10-26 2001-11-13 Lsi Logic Corporation Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer
US6780704B1 (en) 1999-12-03 2004-08-24 Asm International Nv Conformal thin films over textured capacitor electrodes
KR100583157B1 (ko) * 1999-12-22 2006-05-24 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
KR100624903B1 (ko) * 1999-12-22 2006-09-19 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
KR100705926B1 (ko) * 1999-12-22 2007-04-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US6319766B1 (en) 2000-02-22 2001-11-20 Applied Materials, Inc. Method of tantalum nitride deposition by tantalum oxide densification
US7005695B1 (en) 2000-02-23 2006-02-28 Micron Technology, Inc. Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region
US6677640B1 (en) * 2000-03-01 2004-01-13 Micron Technology, Inc. Memory cell with tight coupling
US6346490B1 (en) 2000-04-05 2002-02-12 Lsi Logic Corporation Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps
US6506678B1 (en) 2000-05-19 2003-01-14 Lsi Logic Corporation Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same
US6617206B1 (en) * 2000-06-07 2003-09-09 Micron Technology, Inc. Method of forming a capacitor structure
US6365528B1 (en) 2000-06-07 2002-04-02 Lsi Logic Corporation Low temperature process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric-material characterized by improved resistance to oxidation and good gap-filling capabilities
SE517440C2 (sv) * 2000-06-20 2002-06-04 Ericsson Telefon Ab L M Elektriskt avstämbar anordning och ett förfarande relaterande därtill
US6346488B1 (en) 2000-06-27 2002-02-12 Lsi Logic Corporation Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions
US6368979B1 (en) 2000-06-28 2002-04-09 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6350700B1 (en) 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
KR20020002156A (ko) * 2000-06-29 2002-01-09 박종섭 커패시터 제조방법
US6602753B2 (en) * 2000-07-26 2003-08-05 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film comprising a metal oxide and method of manufacturing the same
US6455424B1 (en) * 2000-08-07 2002-09-24 Micron Technology, Inc. Selective cap layers over recessed polysilicon plugs
US6489242B1 (en) 2000-09-13 2002-12-03 Lsi Logic Corporation Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6391768B1 (en) 2000-10-30 2002-05-21 Lsi Logic Corporation Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
US6537923B1 (en) 2000-10-31 2003-03-25 Lsi Logic Corporation Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6423630B1 (en) 2000-10-31 2002-07-23 Lsi Logic Corporation Process for forming low K dielectric material between metal lines
US6420277B1 (en) 2000-11-01 2002-07-16 Lsi Logic Corporation Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure
US6429497B1 (en) * 2000-11-18 2002-08-06 Hewlett-Packard Company Method for improving breakdown voltage in magnetic tunnel junctions
US6858195B2 (en) 2001-02-23 2005-02-22 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material
US6649219B2 (en) 2001-02-23 2003-11-18 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
JP2002313951A (ja) * 2001-04-11 2002-10-25 Hitachi Ltd 半導体集積回路装置及びその製造方法
JP2002314072A (ja) * 2001-04-19 2002-10-25 Nec Corp 高誘電体薄膜を備えた半導体装置及びその製造方法並びに誘電体膜の成膜装置
US6503840B2 (en) 2001-05-02 2003-01-07 Lsi Logic Corporation Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
US6559048B1 (en) 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
US6583026B1 (en) 2001-05-31 2003-06-24 Lsi Logic Corporation Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
US6562700B1 (en) 2001-05-31 2003-05-13 Lsi Logic Corporation Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal
US6566171B1 (en) 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
US6930056B1 (en) * 2001-06-19 2005-08-16 Lsi Logic Corporation Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
JP3773448B2 (ja) * 2001-06-21 2006-05-10 松下電器産業株式会社 半導体装置
US6559033B1 (en) 2001-06-27 2003-05-06 Lsi Logic Corporation Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6673721B1 (en) 2001-07-02 2004-01-06 Lsi Logic Corporation Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
US6723653B1 (en) 2001-08-17 2004-04-20 Lsi Logic Corporation Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material
US6881664B2 (en) * 2001-08-28 2005-04-19 Lsi Logic Corporation Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
US6816355B2 (en) * 2001-09-13 2004-11-09 Seiko Epson Corporation Capacitor, semiconductor device, electro-optic device, method of manufacturing capacitor, method of manufacturing semiconductor device, and electronic apparatus
US6613665B1 (en) 2001-10-26 2003-09-02 Lsi Logic Corporation Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
US6528423B1 (en) 2001-10-26 2003-03-04 Lsi Logic Corporation Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material
US20050132549A1 (en) * 2001-11-16 2005-06-23 Wong-Cheng Shih Method for making metal capacitors with low leakage currents for mixed-signal devices
JP2003168749A (ja) * 2001-12-03 2003-06-13 Hitachi Ltd 不揮発性半導体記憶装置及びその製造方法
US6790755B2 (en) * 2001-12-27 2004-09-14 Advanced Micro Devices, Inc. Preparation of stack high-K gate dielectrics with nitrided layer
KR100434704B1 (ko) * 2001-12-28 2004-06-07 주식회사 하이닉스반도체 반도체소자의캐패시터 및 그 제조방법
KR20030059388A (ko) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 반도체 메모리 소자의 캐패시터 제조방법
KR100475077B1 (ko) * 2002-05-31 2005-03-10 삼성전자주식회사 캐패시터의 유전막 형성방법
KR100480912B1 (ko) * 2002-06-28 2005-04-07 주식회사 하이닉스반도체 캐패시터 형성 방법
KR100468852B1 (ko) * 2002-07-20 2005-01-29 삼성전자주식회사 캐패시터 구조체 형성 방법
JP4563655B2 (ja) * 2003-04-23 2010-10-13 株式会社日立製作所 半導体装置及びその製造方法
KR100541551B1 (ko) * 2003-09-19 2006-01-10 삼성전자주식회사 적어도 3층의 고유전막들을 갖는 아날로그 커패시터 및그것을 제조하는 방법
JPWO2006028215A1 (ja) * 2004-09-09 2008-05-08 東京エレクトロン株式会社 薄膜キャパシタ及びその形成方法、及びコンピュータ読み取り可能な記憶媒体
JP2006086272A (ja) * 2004-09-15 2006-03-30 Fujitsu Ltd 半導体装置
US7365389B1 (en) 2004-12-10 2008-04-29 Spansion Llc Memory cell having enhanced high-K dielectric
US7863128B1 (en) 2005-02-04 2011-01-04 Spansion Llc Non-volatile memory device with improved erase speed
JP2006245194A (ja) * 2005-03-02 2006-09-14 Mitsui Eng & Shipbuild Co Ltd 半導体装置
US7492001B2 (en) * 2005-03-23 2009-02-17 Spansion Llc High K stack for non-volatile memory
US7294547B1 (en) * 2005-05-13 2007-11-13 Advanced Micro Devices, Inc. SONOS memory cell having a graded high-K dielectric
JP2006324363A (ja) * 2005-05-17 2006-11-30 Elpida Memory Inc キャパシタおよびその製造方法
KR100703838B1 (ko) 2005-06-27 2007-04-06 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 형성방법
US7892964B2 (en) * 2007-02-14 2011-02-22 Micron Technology, Inc. Vapor deposition methods for forming a metal-containing layer on a substrate
JP2009283850A (ja) * 2008-05-26 2009-12-03 Elpida Memory Inc キャパシタ用絶縁膜及びその形成方法、並びにキャパシタ及び半導体装置
WO2010088685A2 (en) * 2009-02-02 2010-08-05 Space Charge, LLC Capacitors using preformed electrode
TWI394189B (zh) * 2009-06-04 2013-04-21 Ind Tech Res Inst 電容基板結構
CN101964254B (zh) * 2009-07-23 2013-04-17 财团法人工业技术研究院 电容基板结构
JP6707995B2 (ja) * 2016-06-01 2020-06-10 株式会社豊田中央研究所 電極構造体、電極構造体を用いる半導体装置及び電極構造体の製造方法
KR102434565B1 (ko) 2018-01-19 2022-08-19 미쓰비시덴키 가부시키가이샤 박층 캐패시터 및 박층 캐패시터의 제조 방법

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1204544A (en) * 1966-09-02 1970-09-09 Hitachi Ltd Semiconductor device and method of manufacturing the same
US3967310A (en) * 1968-10-09 1976-06-29 Hitachi, Ltd. Semiconductor device having controlled surface charges by passivation films formed thereon
JPS4813268B1 (ko) * 1968-10-09 1973-04-26
JPS5258490A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Semiconductor device
US4335391A (en) * 1978-12-11 1982-06-15 Texas Instruments Incorporated Non-volatile semiconductor memory elements and methods of making
JPS5861763A (ja) * 1981-10-09 1983-04-12 武笠　均 触感知器消化装置
JPS59171157A (ja) * 1983-03-18 1984-09-27 Hitachi Ltd 半導体装置
JPS60229233A (ja) * 1984-04-27 1985-11-14 Sumitomo Special Metals Co Ltd 磁気ディスク用基板の製造方法
JPS6148123A (ja) * 1984-08-15 1986-03-08 Sumitomo Special Metals Co Ltd 記録デイスク用基板の製造方法
JPS61145854A (ja) * 1984-12-20 1986-07-03 Fujitsu Ltd 半導体装置
JP2617457B2 (ja) * 1985-11-29 1997-06-04 株式会社日立製作所 半導体装置およびその製造方法
JPS62209832A (ja) * 1986-03-10 1987-09-16 Sanyo Electric Co Ltd 絶縁膜の形成方法
JPS62219659A (ja) * 1986-03-20 1987-09-26 Hitachi Ltd Ｍｏｓ型半導体記憶装置
JPS62242331A (ja) * 1986-04-14 1987-10-22 Sony Corp 半導体装置
JPS6338248A (ja) * 1986-08-04 1988-02-18 Hitachi Ltd 半導体装置およびその製造方法
DE68926793T2 (de) * 1988-03-15 1997-01-09 Toshiba Kawasaki Kk Dynamischer RAM
JP2654393B2 (ja) * 1988-05-16 1997-09-17 株式会社日立製作所 半導体装置
US5091761A (en) * 1988-08-22 1992-02-25 Hitachi, Ltd. Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
US5111355A (en) * 1990-09-13 1992-05-05 National Semiconductor Corp. High value tantalum oxide capacitor
JPH04184932A (ja) * 1990-11-20 1992-07-01 Sony Corp パッシベーション膜の形成方法
JP3047256B2 (ja) * 1991-06-13 2000-05-29 株式会社豊田中央研究所 誘電体薄膜
US5173835A (en) * 1991-10-15 1992-12-22 Motorola, Inc. Voltage variable capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411735B1 (ko) * 2001-07-09 2003-12-18 일성기계공업 주식회사 건조기의 열풍 분사노즐 조립구조

Also Published As

Publication number Publication date
US5688724A (en) 1997-11-18
JPH0677402A (ja) 1994-03-18
KR100267440B1 (ko) 2000-10-16

Similar Documents

Publication Publication Date Title
KR940006246A (ko) 반도체 디바이스용 유전체 구조 및 그 제조방법
KR960002804A (ko) 반도체장치 및 그 제조방법
KR970067977A (ko) 전극의 제조방법
JPH05235275A (ja) 集積回路装置
KR100225848B1 (ko) 커패시터 및 커패시터의 제조 방법
KR950007037A (ko) 반도체 소자의 게이트 절연막 제조방법
KR950004548A (ko) 반도체소자 제조방법
KR970018211A (ko) 반도체 소자의 스페이서 형성방법
KR930001494A (ko) 반도체 소자의 커패시터 제조방법
KR940018930A (ko) 반도체 소자의 평탄화 방법
KR930003255A (ko) 반도체 장치 제조 방법
KR960026966A (ko) 트랜지스터의 게이트 구조 및 그 제조방법
KR890001170A (ko) 반도체 장치의 폴리사이드 구조 제조방법
KR970054050A (ko) 반도체장치의 커패시터 제조방법
KR910020935A (ko) 커패시터 특성을 갖는 반도체 제조방법
KR970063737A (ko) 반도체 장치의 커패시터 제조 방법
KR970054121A (ko) 반도체소자의 캐패시터 형성방법
KR930001353A (ko) 바이모스 제조방법
KR950025874A (ko) 반도체소자의 게이트전극 제조방법
KR19980055937A (ko) 반도체 소자의 모스 캐패시터 제조방법
KR970053983A (ko) Cob 구조를 구비한 dram 셀의 캐패시터 제조방법
KR940022698A (ko) 디램 셀 커패시터 스토리지 노드 콘택홀 형성방법
KR960026837A (ko) 반도체 장치의 커패시터 형성방법
KR970072455A (ko) 박막트랜지스터 제조방법
KR940010390A (ko) 반도체 장치의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120628

Year of fee payment: 13

EXPY Expiration of term