KR900001003A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR900001003A
KR900001003A KR1019890008345A KR890008345A KR900001003A KR 900001003 A KR900001003 A KR 900001003A KR 1019890008345 A KR1019890008345 A KR 1019890008345A KR 890008345 A KR890008345 A KR 890008345A KR 900001003 A KR900001003 A KR 900001003A
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South Korea
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forming
film
wiring portion
selectively
manufacturing
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KR1019890008345A
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English (en)
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KR920004226B1 (ko
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후미토모 마츠오카
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아오이 죠이치
가부시키가이샤 도시바
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Publication of KR900001003A publication Critical patent/KR900001003A/ko
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Publication of KR920004226B1 publication Critical patent/KR920004226B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 반도체장치의 제조방법의 1실시예를 나타낸 공정단면도.

Claims (4)

  1. 반도체기판(1)상에 소자영역 및 소자분리영역(2)을 형성시키는 공정과; 상기 소자영역 및 소자분리영역(2)상에 게이트산화막(3)을 형성시키는 공정 ; 상기 게이트산화막(3)상에 다결정실리콘막(4)을 성장시킨 다음 패터닝을 하여 상기 소자영역상에는 게이트전극(4a)을, 상기 소자분리영역(2)상의 소정부분에는 배선부(4b)를 형성시키는 공정 ; 상기 게이트전극(4a) 및 배선부(4b)를 마스크로 사용하여 상기 소자영역상에 확산층영역(7a, 7b)을 형성시키는 공정 ; 상기 반도체기판(1)의 패턴형성면상에 층간절연막(8)을 형성시키는 공정 ; 상기 반도체기판(1)외 패턴형성면상에 층간절연막(8)을 형성시키는 공정 ; 상기 층간절연막(8)을 선택적으로 제거하여, 배선부(4b, 13)와 확산층영역(7b, 7a)을 각각 직접 접속시키기 위한 접속구멍(9, 10) 및, 상기 배선부(4b)와의 접속구멍(11)을 형성시키는 공정 ; 상기 접속구멍(9, 10, 11)의 밑부분에 선택적으로 금속막(12)을 형성시키는 공정을 구비하여 구성된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 상기 배선부(4b, 13)와 확산층영역(7b, 7a)을 각각 직접 접속시키는 접속구멍(9, 10)과 상기 배선부(4b)와의 접속구멍(11)을 동시에 형성시키도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 1 항에 있어서, 선택적으로 금속막(12)을 형성시키기 위한 공정으로서 텅스텐의 화학적 기상성장법을 이용하도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제 1 항에 있어서, 선택적으로 금속막(12)을 형성시키기 위한 공정으로서 티타늄막을 성장시킨 다음 열처리를 하여 선택적으로 티타늄-실리사이드화하는 방법을 이용하도록 된 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890008345A 1988-06-16 1989-06-16 반도체장치의 제조방법 KR920004226B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-149152 1988-06-16
JP14915288 1988-06-16

Publications (2)

Publication Number Publication Date
KR900001003A true KR900001003A (ko) 1990-01-31
KR920004226B1 KR920004226B1 (ko) 1992-05-30

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KR1019890008345A KR920004226B1 (ko) 1988-06-16 1989-06-16 반도체장치의 제조방법

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US (1) US5053349A (ko)
KR (1) KR920004226B1 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020020614A (ko) * 2000-09-09 2002-03-15 최재승 곡주(穀酒-醱酵酒.)의 산패(酸敗) 지연 양조법
KR20030008745A (ko) * 2001-07-19 2003-01-29 윤재범 돈육 함유 김치의 제조방법
KR102309041B1 (ko) * 2020-12-04 2021-10-06 한국식품연구원 김치 골마지 억제 소재 선발 및 이를 이용한 김치 적용용 조성물 개발

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US5124280A (en) * 1991-01-31 1992-06-23 Sgs-Thomson Microelectronics, Inc. Local interconnect for integrated circuits
JP2675713B2 (ja) * 1991-05-10 1997-11-12 株式会社東芝 半導体装置及びその製造方法
US5726463A (en) * 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
JP2720796B2 (ja) * 1994-11-15 1998-03-04 日本電気株式会社 半導体装置の製造方法
US5536683A (en) * 1995-06-15 1996-07-16 United Microelectronics Corporation Method for interconnecting semiconductor devices
US5554549A (en) * 1995-07-03 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Salicide process for FETs
US5679607A (en) * 1995-08-11 1997-10-21 Winbond Electronics Corp. Method of manufacturing a damage free buried contact using salicide technology
US5612239A (en) * 1995-08-24 1997-03-18 United Microelectronics Corporation Use of oxide spacers formed by liquid phase deposition
KR0186070B1 (ko) * 1995-12-28 1999-03-20 문정환 반도체 메모리 구조 및 그 제조방법
US5895243A (en) * 1996-04-16 1999-04-20 Micron Technology, Inc. Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
US5834811A (en) * 1996-06-17 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide process for FETs
US6027973A (en) * 1997-12-09 2000-02-22 Advanced Micro Devices Oxidation and etchback process for forming thick contact area on polysilicon layer in microelectronic structure
EP1134798A1 (de) * 2000-03-15 2001-09-19 Infineon Technologies AG Halbleiter-Bauelement, Verfahren zu seiner Herstellung und Verfahren zur Herstellung von elektrischen Verbindungen in bzw. auf einem Halbleiter-Substrat
US6406985B1 (en) * 2000-11-15 2002-06-18 United Microelectronics Corp. Method of fabricating buried contact
JP4481557B2 (ja) 2002-07-17 2010-06-16 Ｏｋｉセミコンダクタ株式会社 不揮発性半導体記憶装置の製造方法
US8178902B2 (en) 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020020614A (ko) * 2000-09-09 2002-03-15 최재승 곡주(穀酒-醱酵酒.)의 산패(酸敗) 지연 양조법
KR20030008745A (ko) * 2001-07-19 2003-01-29 윤재범 돈육 함유 김치의 제조방법
KR102309041B1 (ko) * 2020-12-04 2021-10-06 한국식품연구원 김치 골마지 억제 소재 선발 및 이를 이용한 김치 적용용 조성물 개발

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KR920004226B1 (ko) 1992-05-30
US5053349A (en) 1991-10-01

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