KR930003256A - 반도체 집적 회로에 금속화 배선층을 형성하는 방법 - Google Patents
반도체 집적 회로에 금속화 배선층을 형성하는 방법 Download PDFInfo
- Publication number
- KR930003256A KR930003256A KR1019920009265A KR920009265A KR930003256A KR 930003256 A KR930003256 A KR 930003256A KR 1019920009265 A KR1019920009265 A KR 1019920009265A KR 920009265 A KR920009265 A KR 920009265A KR 930003256 A KR930003256 A KR 930003256A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- integrated circuit
- semiconductor integrated
- tiw
- wiring layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 3
- 239000012212 insulator Substances 0.000 claims 3
- 239000011229 interlayer Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 2
- 229910018594 Si-Cu Inorganic materials 0.000 claims 1
- 229910008465 Si—Cu Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000011261 inert gas Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 한 예에서 열처리에 사용되는 어니일러(annealer)램프를 표시하는 약도,
제2도는 본 발명의 보기에서 열처리를 받는 Al 또는 Al합금의 온도 분포.
Claims (3)
- (a)기본 장치를 가지는 Si기판상에 중간막 절연체를 형성하고, (b)Si기판의 표면 밑의 상기 중간막 절연체를 통하여 늘어나는 콘택트홀을 형성하고, 그리고 상기 콘택트홀의 바닥을 구성하는 표면을 TiW 또는 TiN막으로 순차적으로 퇴적되고, (c)상기 콘랙트홀의 상기 TiW 또는 TiN막상에서 뿐만 아니라 상기 중간막 절연체상에 Al 또는 Al합금막을 퇴적하고, 그리고 (d)고압 불활성 가스대기에서, 초음파에 의해 같은 것을 진동하게 하는 동안, 상기 Al또는 Al합금막이 용융되는 온도에 이리하여 처리된 기판을 가열하는 스탭을 포함하는 반도체 집적회로에 금속화 배선층을 형성하는 방법.
- 제1항에 있어서, 상기 TiW 또는 TiN막의 두께는 2000∼3000Å 두께 정도인 반도체 집적 회로에 금속화 배선층을 형성하는 방법.
- 제2항에 있어서, 상기 Al합금막은 Al-Si-Cu 또는 Al-Si-Pd로 형성되는 반도체 집적 회로에 금속에 금속화 배선층을 형성하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3177017A JP2718842B2 (ja) | 1991-07-17 | 1991-07-17 | 半導体集積回路用配線金属膜の製造方法 |
JP91-177017 | 1991-07-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930003256A true KR930003256A (ko) | 1993-02-24 |
KR100231766B1 KR100231766B1 (ko) | 1999-11-15 |
Family
ID=16023706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920009265A KR100231766B1 (ko) | 1991-07-17 | 1992-05-29 | 반도체집적회로의 배선용 금속층의 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5219790A (ko) |
JP (1) | JP2718842B2 (ko) |
KR (1) | KR100231766B1 (ko) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5358574A (en) * | 1993-11-22 | 1994-10-25 | Midwest Research Institute | Dry texturing of solar cells |
US5429985A (en) * | 1994-01-18 | 1995-07-04 | Midwest Research Institute | Fabrication of optically reflecting ohmic contacts for semiconductor devices |
EP0692551A1 (en) * | 1994-07-15 | 1996-01-17 | Applied Materials, Inc. | Sputtering apparatus and methods |
KR960042974A (ko) * | 1995-05-23 | 1996-12-21 | ||
US5610103A (en) * | 1995-12-12 | 1997-03-11 | Applied Materials, Inc. | Ultrasonic wave assisted contact hole filling |
JP2891161B2 (ja) * | 1996-02-15 | 1999-05-17 | 日本電気株式会社 | 配線形成方法 |
US5712207A (en) * | 1996-02-29 | 1998-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Profile improvement of a metal interconnect structure on a tungsten plug |
US6372520B1 (en) * | 1998-07-10 | 2002-04-16 | Lsi Logic Corporation | Sonic assisted strengthening of gate oxides |
JP3631392B2 (ja) | 1998-11-02 | 2005-03-23 | 株式会社神戸製鋼所 | 配線膜の形成方法 |
US6159853A (en) * | 1999-08-04 | 2000-12-12 | Industrial Technology Research Institute | Method for using ultrasound for assisting forming conductive layers on semiconductor devices |
JP4578755B2 (ja) * | 2000-05-02 | 2010-11-10 | 日揮触媒化成株式会社 | 集積回路の製造方法 |
KR20030002787A (ko) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 플러그 형성방법 |
DE10220684B4 (de) * | 2002-05-10 | 2011-12-08 | Enthone Inc. | Verwendung eines Verfahrens zur Herstellung leitender Polymere mit hoher Metallisierungsfähigkeit zur Durchmetallisierung von kaschierten Basismaterialien zur Leiterplattenherstellung |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62296509A (ja) * | 1986-06-17 | 1987-12-23 | Fujitsu Ltd | 半導体装置の製造方法 |
US4920070A (en) * | 1987-02-19 | 1990-04-24 | Fujitsu Limited | Method for forming wirings for a semiconductor device by filling very narrow via holes |
US4758533A (en) * | 1987-09-22 | 1988-07-19 | Xmr Inc. | Laser planarization of nonrefractory metal during integrated circuit fabrication |
JPH02170420A (ja) * | 1988-12-22 | 1990-07-02 | Nec Corp | 半導体素子の製造方法 |
US4997518A (en) * | 1989-03-31 | 1991-03-05 | Oki Electric Industry Co., Ltd. | Method for forming an electrode layer by a laser flow technique |
DE9004951U1 (de) * | 1990-05-01 | 1990-07-05 | Röder GmbH Sitzmöbelwerke, 6000 Frankfurt | Arbeitsstuhl mit einem Sitzträger und einem Rückenlehnenträger |
-
1991
- 1991-07-17 JP JP3177017A patent/JP2718842B2/ja not_active Expired - Lifetime
-
1992
- 1992-04-21 US US07/871,758 patent/US5219790A/en not_active Expired - Lifetime
- 1992-05-29 KR KR1019920009265A patent/KR100231766B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5219790A (en) | 1993-06-15 |
KR100231766B1 (ko) | 1999-11-15 |
JP2718842B2 (ja) | 1998-02-25 |
JPH0529251A (ja) | 1993-02-05 |
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