KR930024103A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR930024103A
KR930024103A KR1019920008292A KR920008292A KR930024103A KR 930024103 A KR930024103 A KR 930024103A KR 1019920008292 A KR1019920008292 A KR 1019920008292A KR 920008292 A KR920008292 A KR 920008292A KR 930024103 A KR930024103 A KR 930024103A
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KR
South Korea
Prior art keywords
semiconductor device
layer
manufacturing
conductor layer
point
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KR1019920008292A
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English (en)
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KR950006343B1 (ko
Inventor
전영권
이창재
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019920008292A priority Critical patent/KR950006343B1/ko
Priority to TW082101112A priority patent/TW331018B/zh
Priority to US08/033,043 priority patent/US5397743A/en
Priority to DE4311509A priority patent/DE4311509C2/de
Priority to JP5136960A priority patent/JPH0653326A/ja
Publication of KR930024103A publication Critical patent/KR930024103A/ko
Application granted granted Critical
Publication of KR950006343B1 publication Critical patent/KR950006343B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층배선 구조의 접속기둥을 신뢰성 있게 형성할 수 있도록한 반도체장치의 제조방법에 관한 것으로, 종래에는 Al과 W을 패터닝할때 식각 가스를 교체해야 하는 불편함이 있으며 교체시기가 정확하지 않으면 배선막의 형상이 불규칙하게 되는 결점이 있었으나, 본 발명에서는 공정을 단순화시키면서도 신뢰성 있는 다층배선을 할 수 있도록 하여 상기 결점을 개선시킬 수 있는 것이다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 다층배선 제조를 나타낸 공정 단면도. 제6도는 제5도 (H)의 사시도. 제7도는 본 발명의 다른 두실시예를 나타낸 단면도.

Claims (11)

  1. 기판위에 차례로 제1절연체층, 제1도전체층을 형성하고 제1도전체 층을 선택적으로 제거하여 제1배선층을 형성하는 공정과, 전표면에 제2절연체층을 형성하고 선택적으로 제거하여 접촉구멍을 형성한 후 접촉구멍이 도포되도록 고융점 반도체층을 증착하여 접속기둥을 형성하는 공정과, 전표면에 차례로 제3절연체층, 제4절연체층을 형성하고 제4연체층을 평탄화한 후 고융점 반도체층의 표면이 노출되도록 에치백하고 전표면에 제2도전체층을 증착하여 제2배선층을 형성하는 공정을 차례로 실시하여 이루어짐을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 제1절연체층으로 산화막을 성장시켜 사용함을 특징으로 하는 반도체 장치의 제조방법.
  3. 제1항에 있어서, 제2도전체층으로 Al을 사용함을 특징으로 하는 반도체 장치의 제조방법.
  4. 제1항에 있어서, 제2절연체층의 두께는 0.5㎛ 이하가 되도록함을 특징으로 하는 반도체 장치의 제조방법.
  5. 제1항에 있어서, 고율점 도전체층으로 고융점 금속 실리사이드를 사용함을 특징으로 하는 반도체 장치의 제조방법.
  6. 제1항에 있어서, 고융점 도전체층으로 Al 합금을 사용함을 특징으로 하는 반도체 장치의 제조방법.
  7. 제1항에 있어서, 제4절연체층으로 산화막을 사용함을 특징으로 하는 반도체 장치의 제조방법.
  8. 제1항에 있어서, 제4절연체층으로 폴리이미드를 사용함을 특징으로 하는 반도체 장치의 제조방법.
  9. 제1항에 있어서,고융점 반도체층은 고율점 도전체층 이하의 온도에서 불황성 가스 분위기로 열처리하여 평탄화됨을 특징으로 하는 3반도체 장치의 제조방법.
  10. 제1항에 있어서, 고율점 도전체층은 고율점 도전체층 이하의 온도에서 H2를 포함하는 가스 분위기로 열처리하여 평탄화됨을 특징으로 하는 반도체장치의 제조방법.
  11. 제1항에 있어서, 제3절연체층에 측벽을 형성한후 에치백함을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920008292A 1992-05-16 1992-05-16 반도체 장치의 제조방법 KR950006343B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019920008292A KR950006343B1 (ko) 1992-05-16 1992-05-16 반도체 장치의 제조방법
TW082101112A TW331018B (en) 1992-05-16 1993-02-17 Method of fabricating semiconductor devices
US08/033,043 US5397743A (en) 1992-05-16 1993-03-18 Method of making a semiconductor device
DE4311509A DE4311509C2 (de) 1992-05-16 1993-04-07 Verfahren zum Herstellen eines Halbleiterbauelements
JP5136960A JPH0653326A (ja) 1992-05-16 1993-05-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920008292A KR950006343B1 (ko) 1992-05-16 1992-05-16 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR930024103A true KR930024103A (ko) 1993-12-21
KR950006343B1 KR950006343B1 (ko) 1995-06-14

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KR1019920008292A KR950006343B1 (ko) 1992-05-16 1992-05-16 반도체 장치의 제조방법

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US (1) US5397743A (ko)
JP (1) JPH0653326A (ko)
KR (1) KR950006343B1 (ko)
DE (1) DE4311509C2 (ko)
TW (1) TW331018B (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0140646B1 (ko) * 1994-01-12 1998-07-15 문정환 반도체장치의 제조방법
US5597764A (en) * 1996-07-15 1997-01-28 Vanguard International Semiconductor Corporation Method of contact formation and planarization for semiconductor processes
US6054340A (en) * 1997-06-06 2000-04-25 Motorola, Inc. Method for forming a cavity capable of accessing deep fuse structures and device containing the same
KR100602131B1 (ko) * 2004-12-30 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조방법

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Also Published As

Publication number Publication date
DE4311509A1 (de) 1993-11-18
US5397743A (en) 1995-03-14
DE4311509C2 (de) 1996-04-04
TW331018B (en) 1998-05-01
JPH0653326A (ja) 1994-02-25
KR950006343B1 (ko) 1995-06-14

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