DE4135810C2 - Halbleitereinrichtung mit einem Zwischenschichtisolierfilm und Verfahren zu deren Herstellung - Google Patents
Halbleitereinrichtung mit einem Zwischenschichtisolierfilm und Verfahren zu deren HerstellungInfo
- Publication number
- DE4135810C2 DE4135810C2 DE4135810A DE4135810A DE4135810C2 DE 4135810 C2 DE4135810 C2 DE 4135810C2 DE 4135810 A DE4135810 A DE 4135810A DE 4135810 A DE4135810 A DE 4135810A DE 4135810 C2 DE4135810 C2 DE 4135810C2
- Authority
- DE
- Germany
- Prior art keywords
- oxide layer
- silicon oxide
- layer
- atmospheric pressure
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
Claims (10)
- 1. einem Halbleitersubstrat (11);
- 2. einem auf dem Halbleitersubstrat (11) gebildeten stufen förmigen Muster (13) aus leitendem Material; und
- 3. einem Zwischenschichtisolierfilm (24) mit vier Silizi
umoxidschichten mit:
- 1. einer auf dem Halbleitersubstrat (11) gebildeten und die Oberfläche des stufenförmigen Musters (13) bedeckenden ersten Siliziumoxidschicht (15) mit we nig SiOH-Bindungen und hoher Bruch- und Rißfestig keit;
- 2. einer auf der Oberfläche der ersten Siliziumoxid schicht (15) abgeschiedenen, die Vertiefungen (15a) in der ersten Siliziumoxidschicht (15) ausfüllenden und das stufenförmige Muster (13) mit einer Schichtdicke (t2) von weniger als 0,2 µm auf dem Mu ster (13) bedeckenden bei Atmosphärendruck unter Benutzung einer organischen Siliziumverbindung und Ozon hergestellten zweiten Siliziumoxidschicht (16), die mehr SiOH-Bindungen als die erste Silizi umoxidschicht (15) und eine sehr gute Stufenbedec kung aufweist;
- 3. einer Vertiefungsabschnitte (16a) auf der Oberflä che der zweiten Siliziumoxidschicht (16) ausfül lenden und zum Einebnen der Oberfläche der zweiten Siliziumoxidschicht (16) dienenden dritten Silizi umoxidschicht (17), die mehr SiOH-Bindungen als die zweite Siliziumoxidschicht (16) und sehr gutes Aus füllungsvermögen für Vertiefungen aufweist; und
- 4. einer auf dem Halbleitersubstrat (11) einschließ lich der zweiten und dritten Siliziumoxidschicht (16, 17) gebildeten vierten Siliziumoxidschicht (18) mit einer Dicke derart, daß die Schichtdicke des aus der ersten, zweiten, dritten und vierten Siliziumoxidschicht (15, 16, 17, 18) gebildeten Zwischenschichtisolierfilmes (24) etwa 0,9 µm ist.
- a) Bilden eines stufenförmigen Musters (13) aus einem lei tenden Material auf einem Halbleitersubstrat (11);
- b) Bilden einer ersten Siliziumoxidschicht (15) mit wenig SiOH-Bindungen und hoher Bruch- und Rißfestigkeit auf dem Halbleitersubstrat (11), so daß die Oberfläche des stufenförmigen Musters (13) abgedeckt wird;
- c) Abscheiden einer zweiten Siliziumoxidschicht (16) aus einer organischen Siliziumverbindung und Ozon bei Atmo sphärendruck, die mehr SiOH-Bindungen als die erste Siliziumoxidschicht (15) und eine sehr gute Stufenbedec kung aufweist, zum Ausfüllen von vertieften Abschnitten (15a) zwischen dem Muster (13) und zum Bedecken des Mu sters (13) mit einer Schichtdicke (t3) im Bereich von 1,0 bis 1,5 µm;
- d) Rückätzen der zweiten Siliziumoxidschicht (16), bis die Schichtdicke (t2) auf dem Muster (13) kleiner als 0,2 µm wird;
- e) Ausfüllen vertiefter Abschnitte (16a) in der Oberfläche der rückgeätzten zweiten Siliziumoxidschicht (16) mit einer dritten Siliziumoxidschicht (17), die mehr SiOH- Bindungen als die zweite Siliziumoxidschicht (16) und ein sehr gutes Ausfüllungsvermögen für Vertiefungen auf weist; und
- f) Abscheiden einer vierten Siliziumoxidschicht (18) auf dem Halbleitersubstrat (11) einschließlich der zweiten und dritten Siliziumoxidschicht (16, 17), bis die Ge samtdicke der ersten, zweiten, dritten und vierten Sili ziumoxidschicht (15, 16, 17, 18) etwa 0,9 µm beträgt.
- 1. Ausfüllen der auf der Oberfläche der zweiten Silizium oxidschicht (16) nach deren Ätzen vorhandenen vertieften Abschnitte
- 2. Aufbringen eines aufgeschleuderten Glases (17) auf die zweite Siliziumoxidschicht (16) zur Bedeckung der zwei ten Siliziumoxidschicht (16) und
- 3. Ätzen der aufgeschleuderten Glasschicht (17) mit dem Er gebnis, daß die aufgeschleuderte Glasschicht (17) nur in den vertieften Abschnitten (16a) verbleibt.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4143592A DE4143592C2 (de) | 1990-10-30 | 1991-10-30 | Verfahren zur Herstellung einer Halbleitereinrichtung mit einem Zwischenschichtisolierfilm |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2294423A JP2640174B2 (ja) | 1990-10-30 | 1990-10-30 | 半導体装置およびその製造方法 |
DE4143592A DE4143592C2 (de) | 1990-10-30 | 1991-10-30 | Verfahren zur Herstellung einer Halbleitereinrichtung mit einem Zwischenschichtisolierfilm |
Publications (2)
Publication Number | Publication Date |
---|---|
DE4135810A1 DE4135810A1 (de) | 1992-05-07 |
DE4135810C2 true DE4135810C2 (de) | 2000-04-13 |
Family
ID=25910633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE4135810A Expired - Fee Related DE4135810C2 (de) | 1990-10-30 | 1991-10-30 | Halbleitereinrichtung mit einem Zwischenschichtisolierfilm und Verfahren zu deren Herstellung |
Country Status (1)
Country | Link |
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DE (1) | DE4135810C2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950006343B1 (ko) * | 1992-05-16 | 1995-06-14 | 금성일렉트론주식회사 | 반도체 장치의 제조방법 |
JPH0766287A (ja) * | 1993-08-23 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US5503882A (en) * | 1994-04-18 | 1996-04-02 | Advanced Micro Devices, Inc. | Method for planarizing an integrated circuit topography |
EP0948035A1 (de) * | 1998-03-19 | 1999-10-06 | Applied Materials, Inc. | Verfahren zum Anbringen einer dielektrischen Deckschicht über einem dielektrischen Stapel |
JP6937724B2 (ja) | 2018-06-21 | 2021-09-22 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01185947A (ja) * | 1988-01-21 | 1989-07-25 | Sharp Corp | 半導体装置製造方法 |
US4962063A (en) * | 1988-11-10 | 1990-10-09 | Applied Materials, Inc. | Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing |
JPH02260534A (ja) * | 1988-12-20 | 1990-10-23 | Hyundai Electron Ind Co Ltd | 紫外線を利用したスピン・オン・ガラス薄膜の硬化方法 |
-
1991
- 1991-10-30 DE DE4135810A patent/DE4135810C2/de not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01185947A (ja) * | 1988-01-21 | 1989-07-25 | Sharp Corp | 半導体装置製造方法 |
US5079188A (en) * | 1988-01-21 | 1992-01-07 | Sharp Kabushiki Kaisha | Method for the production of a semiconductor device |
US4962063A (en) * | 1988-11-10 | 1990-10-09 | Applied Materials, Inc. | Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing |
JPH02260534A (ja) * | 1988-12-20 | 1990-10-23 | Hyundai Electron Ind Co Ltd | 紫外線を利用したスピン・オン・ガラス薄膜の硬化方法 |
US4983546A (en) * | 1988-12-20 | 1991-01-08 | Hyundai Electronics Industries, Co., Ltd. | Method for curing spin-on-glass film by utilizing ultraviolet irradiation |
Non-Patent Citations (8)
Title |
---|
IEEE Electron Device Letters, Vol. 10, No. 12, Dec. 1989, S. 562-564 * |
Int. Electron Devices Meeting 1989, S. 669-672 * |
J. Electrochem. Soc., Vol 137, No. 1, Jan. 1990, S. 190-196 * |
J. Electrochem. Soc., Vol. 137, No. 4, April 1990, S. 1212-1218 * |
J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 133, No. 9, Sept. 1986, S. 1943-1950 * |
J. Vac. Sci. Technol B 8(5), Sept/Ict. 1990, S. 1068-1074 * |
KAWAI, Masato, MABUDA, Kenzo, MIKI, Kazumi and SAKIYAMA, Keizo: Interlayered Dielectric Plana- rization with TEOS-CVD and SOG. In: Fifth Inter- national IEEE VLSI Multilevel Interconnection Conference, Santa Clara, 13.-14.6.1988,pp.419-425 * |
Solid State Technology/April 1988, H. 4, S. 119-122 * |
Also Published As
Publication number | Publication date |
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DE4135810A1 (de) | 1992-05-07 |
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