KR860002141A - 에프롬(EPROM; Erasable Programmable Read Only Memory)장치 - Google Patents

에프롬(EPROM; Erasable Programmable Read Only Memory)장치 Download PDF

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Publication number
KR860002141A
KR860002141A KR1019850005593A KR850005593A KR860002141A KR 860002141 A KR860002141 A KR 860002141A KR 1019850005593 A KR1019850005593 A KR 1019850005593A KR 850005593 A KR850005593 A KR 850005593A KR 860002141 A KR860002141 A KR 860002141A
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South Korea
Prior art keywords
eprom
resin
chip
memory
devices
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KR1019850005593A
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English (en)
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KR900007228B1 (ko
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아끼 히로시 오구
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하시모도 나미오
오끼뎅끼 고오교오 가부시끼 가이샤
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Publication of KR860002141A publication Critical patent/KR860002141A/ko
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Publication of KR900007228B1 publication Critical patent/KR900007228B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/18—Circuits for erasing optically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01011—Sodium [Na]
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    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
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    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Volatile Memory (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

내용 없음

Description

에프롬(EPROM; Erasable Programmabel Read Only Memory)장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 에프롬장치의 일실시예를 도시한 단면도이고,
제2도는 제1도의 요부에 대한 평면도.
제3도는 동 발명자에 의하여 기히 고아된 에프롬장치를 도시한 단면도이다.
* 도면의 주요 부분에 대한 부호의 설명
1:절연성 기판, 2:칩 탑재부, 3:도전성 배선패턴, 4:에프롬 칩, 6:금속세선, 7:중공캡, 9:수지, 9a:제1의 실리콘 수지, 9b:제2의 실리콘수지.

Claims (3)

  1. 주표면상에 도전성 배선패턴이 형성된 절연성 기판의 상기 주표면상 칩 탑재 영역에 에프롬 칩을 배치하고 그 에프롬 칩 상면의 전극을 전기 도전성 배선 패턴에 금속세선에 의하여 배선하고 그 배선부 및 전기 에프롬 칩부를 자외선 투과성의 중공캡으로 복개하여서 된 에프롬 장치에 있어서 적어도 에프롬 칩상에는 자외선 투과성 수지를 사용하여 전기 중공캠내를 수지로 충진하는 것을 특징으로 하는 에프롬 장치.
  2. 제1항에 있어서, 수지는 모두가 자외선 투과성 수지인 것을 특징으로 하는 에프롬 장치.
  3. 제1항에 있어서, 수지는 에프롬 칩 상의 부분이 자외선 투과성의 제1수지이고 기타 부분은 이것과 상이한 제2의 수지인 것을 특징으로 하는 에프롬 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850005593A 1984-08-20 1985-08-02 에프롬(EPROM ; Erasable Programmable Read Only Memory) 장치 KR900007228B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59171453A JPS6150353A (ja) 1984-08-20 1984-08-20 Ｅｐｒｏｍ装置
JP59-171453 1984-08-20

Publications (2)

Publication Number Publication Date
KR860002141A true KR860002141A (ko) 1986-03-26
KR900007228B1 KR900007228B1 (ko) 1990-10-05

Family

ID=15923381

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850005593A KR900007228B1 (ko) 1984-08-20 1985-08-02 에프롬(EPROM ; Erasable Programmable Read Only Memory) 장치

Country Status (4)

Country Link
US (1) US4801998A (ko)
EP (1) EP0175488A3 (ko)
JP (1) JPS6150353A (ko)
KR (1) KR900007228B1 (ko)

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KR100492291B1 (ko) * 2002-10-24 2005-05-30 고준영 내붕괴성이 우수한 토양고화제, 이를 이용한 토양 고화체,제방, 댐

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KR900007228B1 (ko) 1990-10-05
US4801998A (en) 1989-01-31
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JPS6150353A (ja) 1986-03-12
EP0175488A2 (en) 1986-03-26

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