KR910007094A - 수지밀봉형 반도체장치 - Google Patents

수지밀봉형 반도체장치 Download PDF

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Publication number
KR910007094A
KR910007094A KR1019900014334A KR900014334A KR910007094A KR 910007094 A KR910007094 A KR 910007094A KR 1019900014334 A KR1019900014334 A KR 1019900014334A KR 900014334 A KR900014334 A KR 900014334A KR 910007094 A KR910007094 A KR 910007094A
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KR
South Korea
Prior art keywords
semiconductor device
bed portion
lead
semiconductor substrate
metal
Prior art date
Application number
KR1019900014334A
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English (en)
Inventor
데츠야 나카오카
Original Assignee
아오이 죠이치
가부시끼가이샤 도시바
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Publication date
Application filed by 아오이 죠이치, 가부시끼가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910007094A publication Critical patent/KR910007094A/ko
Priority to KR94002040U priority Critical patent/KR940003288Y1/ko

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음

Description

수지 밀봉형 반도체 창치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도는 본 발명에 따른 수지 밀봉형 반도체 장치의 탑재된 상태를 나타낸 상면도.

Claims (1)

  1. 반도체 기판(10)에 형성되는 전극(11)과 이 반도체 기판(10)에 고착되는 금속제 베드부, 반도체 기판(10)의 전극층에 전기적으로 접속되는 금속세선(12), 이 금속세선(12)에 전기적으로 접속되며 상기 금속제 베드부 끝단에 대향하여 배치되는 리이드(13), 금속제 베드부에 형성되는 복스의 각부, 이들을 피복하는 밀봉 수지층을 구비하고 있으며, 금속제 베드부에 형성되는 서로 대향하는 각부에 근접하는 리이드 간격이 다른 리이드 간격보다 넓게 되어 있는 것을 특징으로 하는 수지 밀봉형 반도체 장치.
    ※ 참고 사항 : 최초 출원 내용에 의하여 공개하는 것임.
KR1019900014334A 1989-09-12 1990-09-12 수지밀봉형 반도체장치 KR910007094A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94002040U KR940003288Y1 (en) 1989-09-12 1994-02-03 Plastic packaged semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1236408A JP2637247B2 (ja) 1989-09-12 1989-09-12 樹脂封止型半導体装置
JP1-236408 1989-09-12

Publications (1)

Publication Number Publication Date
KR910007094A true KR910007094A (ko) 1991-04-30

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ID=17000314

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014334A KR910007094A (ko) 1989-09-12 1990-09-12 수지밀봉형 반도체장치

Country Status (5)

Country Link
US (1) US5045919A (ko)
EP (1) EP0419941B1 (ko)
JP (1) JP2637247B2 (ko)
KR (1) KR910007094A (ko)
DE (1) DE69024731T2 (ko)

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US5684332A (en) * 1994-05-27 1997-11-04 Advanced Semiconductor Engineering, Inc. Method of packaging a semiconductor device with minimum bonding pad pitch and packaged device therefrom
JPH09312375A (ja) * 1996-03-18 1997-12-02 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
US6909179B2 (en) * 1996-03-18 2005-06-21 Renesas Technology Corp. Lead frame and semiconductor device using the lead frame and method of manufacturing the same
US5780772A (en) * 1997-01-24 1998-07-14 National Semiconductor Corporation Solution to mold wire sweep in fine pitch devices
KR100265461B1 (ko) * 1997-11-21 2000-09-15 윤종용 더미본딩와이어를포함하는반도체집적회로소자
US6297078B1 (en) 1997-12-31 2001-10-02 Intel Corporation Integrated circuit package with bond wires at the corners of an integrated circuit
US6444295B1 (en) 1998-12-29 2002-09-03 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US6225685B1 (en) * 2000-04-05 2001-05-01 Advanced Micro Devices, Inc. Lead frame design for reduced wire sweep having a defined gap between tie bars and lead pins
KR100642748B1 (ko) * 2004-07-24 2006-11-10 삼성전자주식회사 리드 프레임과 패키지 기판 및 이들을 이용한 패키지
US8035188B2 (en) 2004-07-28 2011-10-11 Panasonic Corporation Semiconductor device
US20060220191A1 (en) * 2005-04-01 2006-10-05 Honeywell International Inc. Electronic package with a stepped-pitch leadframe
JP4879899B2 (ja) * 2005-08-01 2012-02-22 パナソニック株式会社 半導体装置

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JPS62500338A (ja) * 1984-09-27 1987-02-05 モトロ−ラ・インコ−ポレ−テッド 支持リ−ドの改良された構造をもつリ−ドフレ−ムおよびこれを用いる半導体装置
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Also Published As

Publication number Publication date
DE69024731D1 (de) 1996-02-22
EP0419941A3 (en) 1992-10-07
JP2637247B2 (ja) 1997-08-06
EP0419941A2 (en) 1991-04-03
US5045919A (en) 1991-09-03
JPH0399445A (ja) 1991-04-24
EP0419941B1 (en) 1996-01-10
DE69024731T2 (de) 1996-06-27

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