KR910017598A - 반도체 장치의 실장 구조 - Google Patents

반도체 장치의 실장 구조 Download PDF

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Publication number
KR910017598A
KR910017598A KR1019910004443A KR910004443A KR910017598A KR 910017598 A KR910017598 A KR 910017598A KR 1019910004443 A KR1019910004443 A KR 1019910004443A KR 910004443 A KR910004443 A KR 910004443A KR 910017598 A KR910017598 A KR 910017598A
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South Korea
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conductive pattern
chip
circuit board
external circuit
semiconductor chip
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KR1019910004443A
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English (en)
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데루아끼 오구찌
히로미쯔 가네꼬
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야마무라 가쯔미
세이꼬 엡슨 가부시끼가이샤
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Publication of KR910017598A publication Critical patent/KR910017598A/ko

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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/4809Loop shape
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01004Beryllium [Be]
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    • H01L2924/151Die mounting substrate
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    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
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    • H01L2924/181Encapsulation
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    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

내용 없음

Description

반도체 장치의 실장 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 제 1 실시예를 도시하는 단면도, 제 2도는 동 실시예의 수지 봉지전의 평면도, 제 3도는 본 발명의 제 2 실시예를 도시하는 단면도.

Claims (8)

  1. 외부 회로 기판의 도전 패턴으로 감싸여진 비도전면에 칩 면적보다 큰부를 형성하여, 이부의 저면에 반도체 칩을 접착제로 접착하여, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한부내의 반도체 칩 및 그 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
  2. 제 1항에 있어서, 상기한부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
  3. 외부 회로 기판의 비도전면의 칩 접착 영역 이외의 영역에부를 형성하여, 상기 칩 접착 영역에 반도체 칩을 접착제로 접착하여, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한 반도체 칩, 상기한부 및 그들의 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
  4. 제 3항에 있어서, 상기부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
  5. 외부 회로 기판의 비도전면의 칩 접착 영역에 칩면적보다 큰부를 형성하여, 칩 접착 영역에도 부를 형성하여, 이 칩 접착 영역의부의 저면에 반도체 칩을 접착하여, 이 반도체 칩의 상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기 반도체 칩, 2개의부 및 그들의 주변의 패턴의 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
  6. 제 5항에 있어서, 상기한부가 개미홈형상인 것을 특징으로 하는 반도체 장치의 실장구조.
  7. 외부 회로 기판의 도전 패턴으로 감싸인 비도전면을 거친면으로 형성하여, 이 비도전면의 칩 접착 영역에 반도체 칩을 접착제로 접착시켜, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기한 반도체 칩 및 그 주변의 도전 패턴이 일부를 봉지용수지로 봉지하여 형성되는 것을 특징으로 하는 반도체 장치의 실장구조.
  8. 외부 회로 기판의 도전 패턴으로 감싸인 비도전면에 칩면적보다 큰부를 형성하여, 상기 비도전면을 상기부 저면의 칩 부착면을 남겨 거친면으로 형성하여, 상기부 저면의 칩 부착면에 반도체 칩을 접착제로접착시켜, 이 반도체 칩의상 전극과 외부 회로 기판의 도전 패턴을 와이어로 접속하여, 상기부내의 반도체 칩 및 그 주변의 도전 패턴의 일부를 봉지용수지로 봉지하여 구성되는 것을 특징으로 하는 반도체 장치의 실장구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910004443A 1990-03-29 1991-03-21 반도체 장치의 실장 구조 KR910017598A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP78673 1990-03-29
JP7867390A JP2890635B2 (ja) 1990-03-29 1990-03-29 半導体装置

Publications (1)

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KR910017598A true KR910017598A (ko) 1991-11-05

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KR1019910004443A KR910017598A (ko) 1990-03-29 1991-03-21 반도체 장치의 실장 구조

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291792A (ja) * 2000-04-06 2001-10-19 Nec Corp 半導体装置
JP4590961B2 (ja) * 2004-07-20 2010-12-01 株式会社デンソー 電子装置
JP2008192413A (ja) * 2007-02-02 2008-08-21 Nec Tokin Corp 保護回路モジュール
KR101297870B1 (ko) * 2010-05-21 2013-08-19 도요타지도샤가부시키가이샤 반도체 장치
JP6261486B2 (ja) * 2014-10-23 2018-01-17 オリンパス株式会社 実装構造体、撮像モジュールおよび内視鏡装置

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JPH03280452A (ja) 1991-12-11

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