KR960002775A - 수지-봉합(resin-sealed) 반도체 소자 - Google Patents

수지-봉합(resin-sealed) 반도체 소자 Download PDF

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Publication number
KR960002775A
KR960002775A KR1019950016837A KR19950016837A KR960002775A KR 960002775 A KR960002775 A KR 960002775A KR 1019950016837 A KR1019950016837 A KR 1019950016837A KR 19950016837 A KR19950016837 A KR 19950016837A KR 960002775 A KR960002775 A KR 960002775A
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South Korea
Prior art keywords
resin
lead
chip
insulating substrate
sealed semiconductor
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KR1019950016837A
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English (en)
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KR0185247B1 (ko
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유끼히로 쯔지
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가네꼬 히사시
닛본덴기 가부시끼가이샤
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Publication of KR960002775A publication Critical patent/KR960002775A/ko
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Publication of KR0185247B1 publication Critical patent/KR0185247B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 칩-장착부분(2)이 제공된 절연 기판(1), 칩-장착 부분(2)주위에 방사상으로 배치된 리이드(3), 칩-장착 부분(2)에 장착되고 리이드(3)의 내부 리이드(3a)에 전기적으로 연결된 IC칩(5), 절연 기판(1)과 리이드(3)의 외부 리이드(3b)의 가장자리 부분(fringe portion)은 포함하지 않고 IC칩(5)과 내부 리이드(3a)를 포함하는 영역을 밀봉하는 수지(7) 및 수지(7)외부로 튀어나온 외부 리이드가 전기적으로 연결된 외부 단자(8)을 포함하는 수지-봉합 반도체 소자에 관한 것이다.

Description

수지-봉합(resin-sealed) 반도체 소자
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도는 본 발명의 양호한 제1실시예인 수지-봉합 반도체 소자의 전면도, 제2B도는 제2A도에서 A-A´선을 따라 자른 횡단면도,
제3A도는 제2A도와 제2B도에 의한 수지-봉합 반도체 소자를 제조하는데 제공되는 리이드 기판 프레임의 전면도, 제3B도는 제3A도에서 B-B´선을 따라 자른 횡단면도.

Claims (5)

  1. 수지-봉합(resin-sealed) 반도체 소자에 있어서, 상부에 칩-장착(chip-mounting)부분이 제공되는 절연기판; 상기 칩-장착 부분주위에 배치되고, 내부 리이드와 외부 리이드를 가진 리이드; 상기 칩-장착 부분에 장착되고 상기 리이드의 상기 내부 리이드와 전기적으로 연결된 IC칩; 상기 절연 기판의 가장자리 부분(fringe portion)과 리이드으 외부 리이드(3b)는 포함하지 않고 IC칩과 내부 리이드를 포함하는 영역을 밀봉하는 수지; 및 상기 수지 밖으로 튀어나온 상기 외부 리이드와 전기적으로 연결된 외부 단자로 구성된 것을 특징으로 하는 수지-봉합 반도체 소자.
  2. 제1항에 있어서, 상기 수지는 상기 절연 기판의 상부와 하부 표면을 밀봉하는 것을 특징으로 하는 수지-봉합 반도체 소자.
  3. 제1항에 있어서, 상기 수지는 상기 절연 기판의 상부 표면만을 밀봉하는 것을 특징으로 하는 수지-봉합 반도체 소자.
  4. 제1항에 있어서, 상기 절연 기판은 글래스-에폭시 수지(glass-epoxy resins)로 만들어진 것을 특징으로 하는 수지-봉합 반도체 소자.
  5. 제1항에 있어서, 상기 절연 기판은 폴리미드(polymide)수지로 만들어진 것을 특징으로 하는 수지-봉합 반도체 소자.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950016837A 1994-06-23 1995-06-22 수지 밀봉형 반도체 소자의 제조 방법 KR0185247B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-141415 1994-06-23
JP6141415A JP2569400B2 (ja) 1994-06-23 1994-06-23 樹脂封止型半導体装置の製造方法

Publications (2)

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KR960002775A true KR960002775A (ko) 1996-01-26
KR0185247B1 KR0185247B1 (ko) 1999-03-20

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KR1019950016837A KR0185247B1 (ko) 1994-06-23 1995-06-22 수지 밀봉형 반도체 소자의 제조 방법

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US (1) US5606204A (ko)
JP (1) JP2569400B2 (ko)
KR (1) KR0185247B1 (ko)
GB (1) GB2290660B (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6589820B1 (en) * 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
JP4453498B2 (ja) * 2004-09-22 2010-04-21 富士電機システムズ株式会社 パワー半導体モジュールおよびその製造方法
US20060261498A1 (en) * 2005-05-17 2006-11-23 Micron Technology, Inc. Methods and apparatuses for encapsulating microelectronic devices
US7833456B2 (en) * 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
JP6028592B2 (ja) * 2013-01-25 2016-11-16 三菱電機株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018145B2 (ja) * 1980-09-22 1985-05-09 株式会社日立製作所 樹脂封止型半導体装置
JPS60117645A (ja) * 1983-11-30 1985-06-25 Oki Electric Ind Co Ltd Epromの実装構造
JPS61183936A (ja) * 1985-02-08 1986-08-16 Toshiba Corp 半導体装置
JPH07101698B2 (ja) * 1989-07-25 1995-11-01 日本電気株式会社 樹脂封止型半導体装置の製造方法
JPH04146659A (ja) * 1990-10-08 1992-05-20 Matsushita Electron Corp 半導体装置およびその製造方法
JPH0555562U (ja) * 1991-12-24 1993-07-23 沖電気工業株式会社 半導体集積回路装置
US5262927A (en) * 1992-02-07 1993-11-16 Lsi Logic Corporation Partially-molded, PCB chip carrier package
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same

Also Published As

Publication number Publication date
JPH088385A (ja) 1996-01-12
GB2290660B (en) 1998-10-07
JP2569400B2 (ja) 1997-01-08
GB2290660A (en) 1996-01-03
KR0185247B1 (ko) 1999-03-20
GB9512852D0 (en) 1995-08-23
US5606204A (en) 1997-02-25

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