KR890007410A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR890007410A KR890007410A KR1019880013310A KR880013310A KR890007410A KR 890007410 A KR890007410 A KR 890007410A KR 1019880013310 A KR1019880013310 A KR 1019880013310A KR 880013310 A KR880013310 A KR 880013310A KR 890007410 A KR890007410 A KR 890007410A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- inner lead
- semiconductor device
- lead portion
- electrically connected
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1에 의한 ZIP형 패키지의 내부 구조를 도시한 측면도.
제2도는 제1도에 도시한 ZIP형 패키지에 있어서의 리이드 형상을 도시한 측면도.
제3도는 제1도에 도시한 ZIP형 패키지의 외관을 도시한 측면도.
Claims (10)
- 주면과 이면을 갖고, 상기 주면에 동일 기능을 갖는 본딩 패드가 여러쌍 형성된 반도체 칩, 상기 여러개의 본딩 패드 각각에 전기적으로 접속된 여러개의 금속 와이어, 각각이 상기 금속와이어와 접속되어야할 내부 리이드부를 갖는 리이드 프레임, 상기 반도체 칩보다 그 면적이 작고, 상기 반도체 칩을 탑재하기 위한 지지판, 상기 반도체 칩과 상기 지지판 및 상기 내부 리이드의 일부 사이를 전기적으로 절연하고 고착하기 위한 수단, 상기 반도체 칩, 상태 금속 와이어, 상기 리이드 프레임의 내부 리이드부를 포함해서 봉하여 막는 수단으로 되는 ZIP형 패키지의 반도체 장치에 있어서, 상기 동일 기능의 본딩 패드는 그 어느 한쪽이 상기 내부 리이드부와 전기적으로 접속되어 있고, 상기 내부 리이드부의 적어도 1개가 상기 반도체 칩을 지지함과 동시에 상기 본딩 패드와 전기적으로 접속되도록 상기 반도체 칩 이면에 마련되어 있는ZIP형 패키지의 반도체 장치.
- 특허청구의 범위 제1항에 있어서, 상기 반도체 칩과 지지판 내부 리이드의 일부 사이를 전기적으로 절연하고 고착하기 위한 수단으로 폴리이미드계 수지 시트인 ZIP형 패키지의 반도체 장치.
- 특허청구의 범위 제1항에 있어서, 상기 봉하여 막는 수단은 에폭시계 수지인 ZIP형 패키지의 반도체 장치.
- 주면과 이면을 갖고, 상기 주면에 동일 기능을 갖는 본딩 패드가 여러쌍 형성된 반도체 칩, 상기 여러개의 본딩 패드 각각에 전기적으로 접속된 여러개의 금속와이어, 상기 반도체 칩의 둘레에 배치되고, 각각이 금속 와이어와 접속되어야할 내부리이드부를 갖는 리이드 프레임, 상기 반도체 칩을 탑재하기 위한 지지판, 상기 반도체 칩을 상기 지지판 위에 고착하기 위한 수단, 상기 반도체 칩, 상기 금속 와이어, 상기 리이드 프레임의 내부리이드부를 포함해서 봉하여 막는 수단으로 되는 SOJ 패키지의 반도체 장치에 있어서, 상기 동일 기능의 본딩 패드는 어느 한쪽이 상기 내부 리이드부와 전기적으로 접속되어 있는 SOJ형 패키지의 반도체 장치.
- 특허청구의 범위 제4항에 있어서, 상기 지지판은 텝인 SOJ형 패키지의 반도체 장치.
- 특허청구의 범위 제4항에 있어서, 상기 반도체 칩을 지지판위에 고착하기 위한 수단은 은페이스트인 SOJ형 패키지의 반도체 장치.
- 특허청구의 범위 제4항에 있어서, 상기 봉하여 막는 수단은 에폭시계 수지인 SOJ형 패키지의 반도체 장치.
- 주면과 이면을 갖고, 상기 주면에 동일 기능을 갖는 본딩 패드가 여러쌍 형성된 반도체 칩, 상기 여러개의 본딩 패드 각각에 전기적으로 접속된 여러개의 금속 와이어, 각각이 상기 금속 와이어와 접속되어야할 내부 리이드부를 갖는 리이드 프레임, 상기 반도체 칩과 상기 내부 리이드부 사이를 전기적으로 절연하고 고착하기 위한 수단, 상기 반도체 칩, 상기 금속 와이어, 상기 내부 리이드부를 포함해서 봉하여 막는 수단으로 DIP형 패키지의 반도체 장치에 있어서, 상기 동일 기능의 본딩 패드는 그 어느 한족이 상기 내부 리이드부와 전기적으로 접속되고, 상기 내부 리이드부가 상기 반도체 칩을 지지함과 동시에 상기 본딩 패드와 전기적으로 접속되도록 상기 반도체 칩의 이면에 배치되어 있는 DIP형 패키지의 반도체 장치.
- 특허청구의 범위 제8항에 있어서, 상기 반도체 칩과 내부 리이드부 사이를 전기적으로 절연하고 고착하는 수단을 폴리이미드계 수지 시트인 DIP형 패키지의 반도체 장치.
- 특허청구의 범위 제8항에 있어서, 상기 봉하여 막는 수단은 에폭시계 수지인 DIP형 패키지의 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-264679 | 1987-10-20 | ||
JP87-264679 | 1987-10-20 | ||
JP62264679A JP2763004B2 (ja) | 1987-10-20 | 1987-10-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890007410A true KR890007410A (ko) | 1989-06-19 |
KR970006529B1 KR970006529B1 (ko) | 1997-04-29 |
Family
ID=17406695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880013310A KR970006529B1 (ko) | 1987-10-20 | 1988-10-12 | 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US4934820A (ko) |
JP (1) | JP2763004B2 (ko) |
KR (1) | KR970006529B1 (ko) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5365113A (en) * | 1987-06-30 | 1994-11-15 | Hitachi, Ltd. | Semiconductor device |
US5287000A (en) * | 1987-10-20 | 1994-02-15 | Hitachi, Ltd. | Resin-encapsulated semiconductor memory device useful for single in-line packages |
US4990996A (en) * | 1987-12-18 | 1991-02-05 | Zilog, Inc. | Bonding pad scheme |
US5208782A (en) * | 1989-02-09 | 1993-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement |
US5217917A (en) * | 1990-03-20 | 1993-06-08 | Hitachi, Ltd. | Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor |
US5177032A (en) * | 1990-10-24 | 1993-01-05 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5140404A (en) * | 1990-10-24 | 1992-08-18 | Micron Technology, Inc. | Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5276352A (en) * | 1990-11-15 | 1994-01-04 | Kabushiki Kaisha Toshiba | Resin sealed semiconductor device having power source by-pass connecting line |
JP2925337B2 (ja) * | 1990-12-27 | 1999-07-28 | 株式会社東芝 | 半導体装置 |
US5396701A (en) * | 1993-06-29 | 1995-03-14 | Texas Instruments Inc. | Method for packaging an integrated circuit |
US5907769A (en) * | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
US5840598A (en) | 1997-08-14 | 1998-11-24 | Micron Technology, Inc. | LOC semiconductor assembled with room temperature adhesive |
JP3549714B2 (ja) | 1997-09-11 | 2004-08-04 | 沖電気工業株式会社 | 半導体装置 |
US6043558A (en) * | 1997-09-12 | 2000-03-28 | Micron Technology, Inc. | IC packages including separated signal and power supply edge connections, systems and devices including such packages, and methods of connecting such packages |
US6211565B1 (en) | 1999-04-29 | 2001-04-03 | Winbond Electronics Corporation | Apparatus for preventing electrostatic discharge in an integrated circuit |
JP4450530B2 (ja) * | 2001-07-03 | 2010-04-14 | 三菱電機株式会社 | インバータモジュール |
JP2003204009A (ja) * | 2001-11-01 | 2003-07-18 | Sanyo Electric Co Ltd | 半導体装置 |
US6841852B2 (en) * | 2002-07-02 | 2005-01-11 | Leeshawn Luo | Integrated circuit package for semiconductor devices with improved electric resistance and inductance |
JP2006286688A (ja) * | 2005-03-31 | 2006-10-19 | Elpida Memory Inc | 半導体装置 |
US7375415B2 (en) | 2005-06-30 | 2008-05-20 | Sandisk Corporation | Die package with asymmetric leadframe connection |
JP5001449B1 (ja) * | 2011-07-27 | 2012-08-15 | 株式会社大都技研 | 遊技台 |
JP5382825B2 (ja) * | 2012-05-17 | 2014-01-08 | 株式会社大都技研 | 遊技台 |
JP5915877B2 (ja) * | 2015-03-20 | 2016-05-11 | 株式会社大都技研 | 遊技台 |
JP5953465B2 (ja) * | 2015-03-23 | 2016-07-20 | 株式会社大都技研 | 遊技台 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6043849A (ja) * | 1983-08-19 | 1985-03-08 | Fuji Electric Co Ltd | リ−ドフレ−ム |
US4595945A (en) * | 1983-10-21 | 1986-06-17 | At&T Bell Laboratories | Plastic package with lead frame crossunder |
JPS6091344A (ja) * | 1983-10-26 | 1985-05-22 | Toshiba Corp | 原稿台装置 |
JPS6098652A (ja) * | 1983-11-02 | 1985-06-01 | Mitsubishi Electric Corp | 半導体装置 |
JPS60167454A (ja) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | 半導体装置 |
JPS60198835A (ja) * | 1984-03-23 | 1985-10-08 | Nec Corp | 半導体記憶装置 |
US4612564A (en) * | 1984-06-04 | 1986-09-16 | At&T Bell Laboratories | Plastic integrated circuit package |
US4688072A (en) * | 1984-06-29 | 1987-08-18 | Hughes Aircraft Company | Hierarchical configurable gate array |
JPH06105721B2 (ja) * | 1985-03-25 | 1994-12-21 | 日立超エル・エス・アイエンジニアリング株式会社 | 半導体装置 |
-
1987
- 1987-10-20 JP JP62264679A patent/JP2763004B2/ja not_active Expired - Lifetime
-
1988
- 1988-10-12 KR KR1019880013310A patent/KR970006529B1/ko not_active IP Right Cessation
- 1988-10-12 US US07/256,862 patent/US4934820A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2763004B2 (ja) | 1998-06-11 |
US4934820A (en) | 1990-06-19 |
KR970006529B1 (ko) | 1997-04-29 |
JPH01107548A (ja) | 1989-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR890007410A (ko) | 반도체 장치 | |
KR920010853A (ko) | 수지봉지형 반도체장치 | |
KR850700086A (ko) | 집적회로 | |
KR870004507A (ko) | 수지봉지형 반도체 장치 | |
KR970013236A (ko) | 금속 회로 기판을 갖는 칩 스케일 패키지 | |
KR920007132A (ko) | 집적회로용 절연리드 프레임 및 그의 제조방법 | |
KR850002173A (ko) | 집적회로 소자내의 칩 지지패드를 접지시키기 위한방법 | |
KR910007094A (ko) | 수지밀봉형 반도체장치 | |
KR920015525A (ko) | 반도체장치 | |
KR900001004A (ko) | 플라스틱 캡슐형 멀티칩 하이브리드 집적회로 | |
JPS63108761A (ja) | 樹脂封止型半導体装置 | |
JPH06103731B2 (ja) | 半導体パッケ−ジ | |
JPH03129840A (ja) | 樹脂封止型半導体装置 | |
KR930007920Y1 (ko) | 양면 박막회로판을 갖는 이중 패키지 구조 | |
JP2587722Y2 (ja) | 半導体装置 | |
KR930011190A (ko) | 반도체 리드 프레임 | |
KR970030726A (ko) | 리드 프레임을 이용한 볼 그리드 어레이 패키지 | |
KR930014851A (ko) | 리이드 프레임을 갖춘 반도체 패키지 | |
JPS62119933A (ja) | 集積回路装置 | |
KR970013280A (ko) | 더미 패드(dummy pad)를 갖는 리드프레임 및 그를 이용한 칩 패키지 | |
KR870000753A (ko) | 수지봉합형 반도체장치 | |
KR970013233A (ko) | 기판을 이용한 센터 패드(center pad)형태의 칩이 적용된 멀티칩 패키지 | |
JPS62122253A (ja) | 半導体装置 | |
KR920007156A (ko) | 수지밀봉반도체장치 | |
JPS649734B2 (ko) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20010330 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |