JP3549714B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3549714B2
JP3549714B2 JP24653597A JP24653597A JP3549714B2 JP 3549714 B2 JP3549714 B2 JP 3549714B2 JP 24653597 A JP24653597 A JP 24653597A JP 24653597 A JP24653597 A JP 24653597A JP 3549714 B2 JP3549714 B2 JP 3549714B2
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Japan
Prior art keywords
connection
pad
lsi
semiconductor device
portions
Prior art date
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Expired - Fee Related
Application number
JP24653597A
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English (en)
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JPH1187400A (ja
Inventor
正夫 佐々木
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP24653597A priority Critical patent/JP3549714B2/ja
Priority to US09/137,154 priority patent/US20020003309A1/en
Priority to SG1998003300A priority patent/SG70117A1/en
Priority to KR1019980037040A priority patent/KR100336081B1/ko
Publication of JPH1187400A publication Critical patent/JPH1187400A/ja
Priority to US10/041,965 priority patent/US6555923B2/en
Priority to US10/175,860 priority patent/US7344968B2/en
Priority to US10/175,864 priority patent/US6590297B2/en
Application granted granted Critical
Publication of JP3549714B2 publication Critical patent/JP3549714B2/ja
Priority to US11/169,734 priority patent/US7288846B2/en
Priority to US11/169,726 priority patent/US7309915B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
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Description

【０００１】
【発明の属する技術分野】
本発明は、集積回路と外部回路に接続されて該集積回路に信号を入出力するパッド部とを備えた半導体装置（以下、ＬＳＩという）に関するものである。
【０００２】
【従来の技術】
図２（ａ）〜（ｃ）は、従来のＬＳＩ（その１）を示す平面図であり、同図（ａ）はＬＳＩのパッド部のレイアウト図であり、同図（ｂ）は同図（ａ）のＡ部分の拡大図であり、同図（ｃ）は同図（ａ）の接続状態を示す図である。
このＬＳＩ１０には、図示しない集積回路が基板に形成される共に、該集積回路に信号を入出力する複数の配線パタンが形成されている。この複数の配線パタンに端子となる複数のパッド１１が形成されている。ＬＳＩ１０の表面は、保護膜１２で覆われているが、複数のパッド１１の箇所の保護膜１２が除去されて窓１３が形成されている。窓１３と該窓１３から露出したパッド１１とで複数のパッド部１４が構成されている。
これらのパット部１４は、ワイヤボンディング用のパッド部であり、図２（ｃ）のように、パッド部１４の窓１３から露出したパッド１１と外部回路との間がワイヤ１５で接続されることにより、外部回路とＬＳＩ１０とのアッセンブリが行われる。
【０００３】
図３（ａ）〜（ｃ）は、従来のＬＳＩ（その２）を示す平面図であり、同図（ａ）はＬＳＩのパッド部のレイアウト図であり、同図（ｂ）は同図（ａ）のＢ部分の拡大図であり、同図（ｃ）は同図（ａ）の接続状態を示す図である。
このＬＳＩ２０には、例えば前述のＬＳＩ１０と同様の集積回路が基板に形成されると共に、複数の配線パタンが形成されている。この複数の配線パタンに端子となるＬＳＩ１０と同様の複数のパッド１１が形成されている。ＬＳＩ２０の表面は、保護膜２１で覆われているが、各パッド１１の箇所の保護膜２１が除去されて図３（ｂ）のような窓２２が形成され、該窓２２から露出したパッド１１上に、半田等で構成されたバンプ２３が堆積され、保護膜２１の表面からさらに突出している。この窓２２とバンプ２３とで、パッド部２５が構成されている。
これらのパット部２５のバンプ２３を用いて、外部回路２６を直接接続することより、図３（ｃ）のように、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）或いはＣＯＧ（Ｃｈｉｐ Ｏｎ Ｇｌａｓｓ ）方式のアッセンブリが行われる。
【０００４】
【発明が解決しようとする課題】
しかしながら、従来のＬＳＩでは、次のような課題があった。
ＬＳＩ１０，２０は、複数のパッド部１４，２５の構造によって外部回路に対する接続方法が異なるので、該ＬＳＩ１０，２０が、例え同じ集積回路と配線パタンを持ち、同じ動作を行うものであっても、パッド部１４，２５の構造で決まる１種類のアッセンブリしか実施することができなかった。そのため、ワイヤボンドで外部回路と接続するＬＳＩ１０と、ＴＡＢ方式で外部回路の接続をするＬＳＩ２０とを、別々に作製することになり、開発効率及び量産効果を向上できないという課題があった。
【０００５】
【課題を解決するための手段】
前記課題を解決するために、本発明のＬＳＩでは、集積回路が形成された主表面を有する半導体チップと、前記主表面に形成されると共に、前記集積回路の１つの端子に対して信号の入出力を行うパッド部と、前記パッド部に互いに離間して配置され、かつ、バンプが接続される第１の接続部及びワイヤが接続される第２の接続部と、前記パッド部を含む前記主表面を覆い、前記第１の接続部を露出する第１の開口部及び前記第２の接続部を露出する第２の開口部とを有する保護膜とを備えている。
【０００６】
本発明の他のＬＳＩでは、集積回路が形成された主表面を有する半導体チップと、前記主表面に形成されると共に、前記集積回路の１つの端子に対して信号の入出力を行うパッド部とを有している。そして、前記パッド部には、ワイヤを用いた接続を行うための接続部とバンプを用いた接続を行うための接続部との両方が形成され、ワイヤボンディング接続あるいはバンプ接続のいずれにも対応可能になっている。
【０００７】
【発明の実施の形態】
（第１の実施形態）
図１（ａ），（ｂ）は、本発明の第１の実施形態を示すＬＳＩの平面図であり、同図（ａ）はパッド部の配置を示すレイアウト図であり、同図（ｂ）は同図 （ａ）のＣ部分の拡大図である。
このＬＳＩ３０は、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ３０の表面は、保護膜３１で覆われている。複数の配線パタンには、端子となる複数のパッド３２が形成され、該各パッド３２の位置に外部回路に対して信号を入出力するパッド部４０がそれぞれ形成されている。
【０００８】
図４は、図１中のパッド部４０の構造を示す断面図である。
複数のパッド部４０は、共通のパッド３２に対して設けられた第１の接続部４０Ａと第２の接続部４０Ｂとを有している。
接続部４０Ａは、保護膜３１が除去された第２の開口部である第１の窓４１と、パッド３２における該窓４１から露出した部分４２とで構成されている。接続部４０Ｂは、保護膜３１が除去された第１の開口部である第２の窓４３と、パッド３２における窓４３から露出した部分４４と、その部分４４上に堆積されたバンプ電極である導電性部材のバンプ４５とで構成されている。パンプ４５は、例えば銅等の下地層４５ａと、金や半田等の接続層４５ｂとがパッド３２に積層されると共に、保護膜３１から突起して形成されている。
このＬＳＩ３０では、各パッド部４０の接続部４０Ａが基板の中心側を向き、接続部４０Ｂが基板の外側を向くように、複数のパッド部４０がレイアウトされている。
【０００９】
図５（ａ），（ｂ）は、図１の接続例を示す平面図であり、この図５（ａ），（ｂ）を参照しつつ、ＬＳＩ３０の使用方法を説明する。
ＬＳＩ３０のパッド部４０における接続部４０Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０ＢはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ３０をワイヤボンディングで外部回路に接続する要求がある場合には、図５（ａ）のように、各パッド部４０の接続部４０Ａと外部回路との間をワイヤ３５でそれぞれ接続する。ＬＳＩ３０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、接続部４０Ｂにおける接続層４５ｂを、テープや硝子５０に形成された外部回路に直接接続する。
【００１０】
以上のように、この第１の実施形態では、各パッド部４０に、共通のパッド３２に対して外部回路を接続するための２つの接続部４０Ａ，４０Ｂをそれぞれ設け、その接続部４０Ａをワイヤボンディングによって外部回路と接続可能な構造とし、接続部４０ＢをＴＡＢ方式やＣＯＧ方式によって外部回路と接続可能な構造にしたので、ＬＳＩ３０は、複数の実装形態がとれるようになる。そのため、ＬＳＩ３０のパッド部４０の変更を行わなくても、ＬＳＩ３０の完成後に、要求に応じた実装形態を選択すれば、複数のアッセンブリが可能になるので、ＬＳＩ３０の開発効率が向上すると共に、量産効率が向上する。
【００１１】
（第２の実施形態）
図６は、本発明の第２の実施形態を示すＬＳＩの平面図である。
このＬＳＩ６０は、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ６０の表面は、保護膜６１で覆われている。複数の配線パタンには端子となる複数のパッド６２が形成され、該各パッド６２の位置に、外部回路に対して信号を入出力するパッド部７０がそれぞれ形成されている。
各パッド部７０は、図４と同様の構造の第１の接続部４０Ａ及び第２の接続部４０Ｂをそれぞれ有している。ただし、このＬＳＩ６０では、各パッド部７０の接続部４０Ａが基板の外側を向き、接続部４０Ｂが基板の中心側をそれぞれ向くように、複数のパッド部７０がレイアウトされている。
【００１２】
図７（ａ），（ｂ）は、図６の接続例を示す平面図であり、この図７（ａ），（ｂ）を参照しつつ、ＬＳＩ６０の使用方法を説明する。
ＬＳＩ６０のパッド部７０における接続部４０Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０ＢはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ６０をワイヤボンディングで外部回路に接続する要求がある場合には、図７（ａ）のように、各パッド部７０の外側の接続部４０Ａと外部回路との間をワイヤ６５でそれぞれ接続する。さらに、必要に応じて、チップコンデンサ等のデバイス６６，６７を、中心側の接続部４０Ｂに接続して搭載する。
【００１３】
ＬＳＩ６０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、中心側の接続部４０Ｂにおける接続層４５ｂを、テープや硝子５０に形成された外部回路に直接接続する。さらに追加して、ワイヤボンディングで他の外部回路に接続する要求がある場合には、図７（ｂ）のように、外側の接続部４０Ａと外部回路との間をワイヤ６５でそれぞれ接続する。
以上のように、この第２の実施形態のＬＳＩ６０では、各パッド部７０に２つの接続部４０Ａ，４０Ｂをそれぞれ設け、その接続部４０Ａを基板の外側に向け、接続部４０Ｂを中心側に向けてレイアウトしたので、第１の実施形態と同様に、ワイヤボンディングによる外部回路との接続が可能になると共に、ＴＡＢ方式やＣＯＧ方式による外部回路との接続が可能になり、複数の実装形態がとれる。さらに、その両方の実装形態を同時に施すことが可能になり、ＬＳＩ６０の開発効率が向上すると共に、量産効率が向上する。その上、例えばワイヤボンディングによる実装を行った状態で、従来ではＬＳＩ６０の周辺回路に設けていたデバイス６６，６７を該ＬＳＩ６０上に搭載することが可能になり、このＬＳＩ６０を組み込むシステムが小型化できる。
【００１４】
（第３の実施形態）
図８は、本発明の第３の実施形態を示すＬＳＩの平面図である。
このＬＳＩ８０は、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ８０の表面は、保護膜８１で覆われている。複数の配線パタンには端子となる複数のパッド８２が形成され、該各パッド８２の位置に、外部回路に対して信号を入出力する２種類のパッド部９０，１００が適宜形成されている。
図９は、図８中のパッド部１００の構造を示す断面図である。
パッド部９０は、図４と同様の構造の第１の接続部４０Ａ及び第２の接続部４０Ｂをそれぞれ有している。これに対し、パッド部１００は、図９のように、共通のパッド８２に対して設けられた第１の接続部１００Ａと、２つの第２の接続部１００Ｂ，１００Ｃとを備えている。
【００１５】
接続部１００Ａは、保護膜８１が除去された第２の開口部である第１の窓１０１と、パッド８２における該窓１０１から露出した部分１０２とから構成されている。接続部１００Ｂは、保護膜８１が除去された第１の開口部である第２の窓１０３と、パッド８２における窓１０３から露出した部分１０４と、その部分１０４上に堆積されたバンプ電極である導電性部材のバンプ１０５とで構成されている。パンプ１０５は、例えば銅等の下地層１０５ａと、金や半田等の接続層１０５ｂとがパッド８２に積層されて形成されている。接続部１００Ｃは、保護膜８１が除去された第１の開口部である第２の窓１０６と、パッド８２における窓１０６から露出した部分１０７と、その部分１０７上に堆積されたバンプ電極である導電性部材のバンプ１０８とで構成されている。パンプ１０８は、例えば銅等の下地層１０８ａと、金や半田等の接続層１０８ｂとがパッド８２に積層されて保護膜８１から突起して形成されている。
【００１６】
次に、ＬＳＩ８０の使用方法を説明する。
ＬＳＩ８０の各パッド部９０，１００における接続部４０Ａ，１００Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０Ｂ，１００Ｂ，１００ＣはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ８０をワイヤボンディングで外部回路に接続する要求がある場合には、各パッド部９０，１００の接続部４０Ａ，１００Ａと外部回路との間をワイヤ８５でそれぞれ接続する。さらに、必要に応じて、チップコンデンサ等のデバイス８６，８７を、選択された接続部４０Ｂ，１００Ｂ，１００Ｃに直接接続して搭載する。ここで、パッド部１００では、接続部１００Ｂ，１００Ｃを有しているので、２つのデバイス８６，８７の接続が可能になっている。
ＬＳＩ８０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、各パッド９０，１００の接続部４０Ｂ，１００Ｂ，１００Ｃにおける接続層４５ｂ，１０５ｂ，１０８ｂを、テープや硝子に形成された外部回路に直接接続する。さらに追加して、ワイヤボンディングで他の外部回路に接続する要求がある場合には、図７（ｂ）のように、接続部４０Ａと外部回路との間をワイヤ８５でそれぞれ接続する。
【００１７】
以上のように、この第３の実施形態のＬＳＩ８０では、各パッド部９０，１００に２つの接続部４０Ａ，４０Ｂ或いは３つの接続部１００Ａ，１００Ｂ，１００Ｃをそれぞれ設けたので、第１の実施形態と同様に、ワイヤボンディングによる外部回路との接続が可能になると共に、ＴＡＢ方式やＣＯＧ方式によって外部回路との接続が可能なり、複数の実装形態がとれる。さらに、その両方の実施形態を同時に施すことが可能になり、ＬＳＩ８０の開発効率が向上すると共に、量産効率が向上する。その上、例えばワイヤボンディングによる実装を行った状態で、デバイス８６，８７の搭載が可能になるとと共に、１つのパッド部１００に２個のデバイス８６，８７が接続できるので、第２の実施形態よりも、適用可能な実装形態の種類が増加し、該ＬＳＩ８０を組み込むシステムが小型化できる。
なお、本発明は、上記実施形態に限定されず種々の変形が可能である。
例えば、パッド部１００では、ＴＡＢ方式やＣＯＧ方式に適用可能な接続部１００、１００Ｂを設けているが、その数は２個に限定されず、３個以上にしてもよい。また、パッド部１００にワイヤボンディングで接続可能な接続部１００Ａを複数設けてもよい。このようにすると、周辺回路での配線の引き回しが減少し、システムがさらに小型化する。
【００１８】
【発明の効果】
以上詳細に説明したように、本発明によれば、集積回路の１つの端子に対して信号の入出力を行う共通のパッド部に対して第１及び第２の接続部という複数の接続部を設ける構成にしたので、複数の実装形態が選択できるようになり、また、要求に応じた選択を行えば、ＬＳＩの変更を行わなくても要求に応じたアッセンブリが可能となる。これにより、ＬＳＩの開発効率と量産効率とを向上させることが可能となる。その上、本願発明の構成によれば、１つのパッド部こ対してバンプ接続及びワイヤボンディング接続の２つの接続部を設けているので、ワイヤボンディングによって外部回路に接続した状態で、ＬＳＩ上にデバイス（例えば、コンデンサ）を搭載できるようになり、その結果、このＬＳＩを組み込むシステムの小型化を図ることが可能となる。さらに、本願発明のＬＳＩでは、主表面上に形成される、例えばアルミニウム層よりなるパッド部に複数の接続部を配置する構成とすることで、半導体チップに形成される配線抵抗の低減を図り、加工パタンの微細化に伴う信号遅延を回避して高速化を実現するＬＳＩを提供することが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示すＬＳＩの平面図である。
【図２】従来のＬＳＩ（その１）を示す平面図である。
【図３】従来のＬＳＩ（その２）を示す平面図である。
【図４】図１中のパッド部４０を示す断面図である。
【図５】図１の接続例を示す平面図である。
【図６】本発明の第２の実施形態を示すＬＳＩの平面図である。
【図７】図６の接続例を示す平面図である。
【図８】本発明の第３の実施形態を示すＬＳＩの平面図である。
【図９】図８中のパッド部１００を示す断面図である
【符号の説明】
３０，６０，８０ ＬＳＩ
３１，６１，８１ 保護膜
３２，６２，８２ パッド
３５，６５，８５ ワイヤ
４０，７０，９０，１００ パッド部
４０Ａ，１００Ａ 第１の接続部
４０Ｂ，１００Ｂ，１００Ｃ 第２の接続部
４１，４３，１０１，１０３，１０６ 窓（開口部）
４５，１０５，１０８ バンプ
５０ テープ、硝子
６６，６７，８６，８７ デバイス（外部回路）

Claims (12)

  1. 集積回路が形成された主表面を有する半導体チップと、
    前記主表面に形成されると共に、前記集積回路の１つの端子に対して信号の入出力を行うパッド部と、
    前記パッド部に互いに離間して配置され、かつ、バンプが接続される第１の接続部及びワイヤが接続される第２の接続部と、
    前記パッド部を含む前記主表面を覆い、前記第１の接続部を露出する第１の開口部及び前記第２の接続部を露出する第２の開口部とを有する保護膜とを備えたことを特徴とする半導体装置。
  2. 請求項１記載の半導体装置において、前記第１の開口部内に形成されたバンプを有することを特徴とする半導体装置。
  3. 請求項１または２いずれか記載の半導体装置において、前記第１及び第２の接続部を備えるパッド部は前記主表面上に複数個設けられており、前記複数のパッド部は、前記半導体チップの外周に沿って配置されていることを特徴とする半導体装置。
  4. 請求項１または２いずれか記載の半導体装置において、前記パッド部には複数の前記第１の接続部が設けられていることを特徴とする半導体装置。
  5. 請求項１〜４のいずれか１項に記載の半導体装置は、さらに、前記第１の接続部においてバンプを介して搭載されるコンデンサを有することを特徴とする半導体装置。
  6. 請求項５記載の半導体装置において、前記第２の開口部は前記第１の開口部よりも前記半導体チップの周辺近傍に配置されていることを特徴とする半導体装置。
  7. 集積回路が形成された主表面を有する半導体チップと、
    前記主表面に形成されると共に、前記集積回路の１つの端子に対して信号の入出力を行うパッド部とを有し、
    前記パッド部には、ワイヤを用いた接続を行うための接続部とバンプを用いた接続を行うための接続部との両方が形成され、ワイヤボンディング接続あるいはバンプ接続のいずれにも対応可能であることを特徴とする半導体装置。
  8. 請求項７記載の半導体装置において、前記第１の開口部内に形成されたバンプを有することを特徴とする半導体装置。
  9. 請求項７または８いずれか記載の半導体装置において、前記第１及び第２の接続部を備えるパッド部は前記主表面上に複数個設けられており、前記複数のパッド部は、前記半導体チップの外周に沿って配置されていることを特徴とする半導体装置。
  10. 請求項７または８いずれか記載の半導体装置において、前記パッド部には複数の前記第１の接続部が設けられていることを特徴とする半導体装置。
  11. 請求項７〜１０のいずれか１項に記載の半導体装置は、さらに、前記第１の接続部においてバンプを介して搭載されるコンデンサを有することを特徴とする半導体装置。
  12. 請求項１１に記載の半導体装置において、前記第２の開口部は前記第１の開口部よりも前記半導体チップの周辺近傍に記置されていることを特徴とする半導体装置。
JP24653597A 1997-09-11 1997-09-11 半導体装置 Expired - Fee Related JP3549714B2 (ja)

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JP24653597A JP3549714B2 (ja) 1997-09-11 1997-09-11 半導体装置
US09/137,154 US20020003309A1 (en) 1997-09-11 1998-08-20 Semiconductor chip having pads with plural different junction type
SG1998003300A SG70117A1 (en) 1997-09-11 1998-08-25 Semiconductor chip
KR1019980037040A KR100336081B1 (ko) 1997-09-11 1998-09-08 반도체 칩
US10/041,965 US6555923B2 (en) 1997-09-11 2002-01-09 Semiconductor chip having pads with plural junctions for different assembly methods
US10/175,860 US7344968B2 (en) 1997-09-11 2002-06-21 Semiconductor chip having pads with plural junctions for different assembly methods
US10/175,864 US6590297B2 (en) 1997-09-11 2002-06-21 Semiconductor chip having pads with plural junctions for different assembly methods
US11/169,734 US7288846B2 (en) 1997-09-11 2005-06-30 Semiconductor chip having pads with plural junctions for different assembly methods
US11/169,726 US7309915B2 (en) 1997-09-11 2005-06-30 Semiconductor chip having pads with plural junctions for different assembly methods

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