KR920015525A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR920015525A
KR920015525A KR1019920000466A KR920000466A KR920015525A KR 920015525 A KR920015525 A KR 920015525A KR 1019920000466 A KR1019920000466 A KR 1019920000466A KR 920000466 A KR920000466 A KR 920000466A KR 920015525 A KR920015525 A KR 920015525A
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KR
South Korea
Prior art keywords
semiconductor device
die pads
die
side direction
supported
Prior art date
Application number
KR1019920000466A
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English (en)
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KR960005039B1 (ko
Inventor
츠토무 이마무라
이사오 바바
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR920015525A publication Critical patent/KR920015525A/ko
Application granted granted Critical
Publication of KR960005039B1 publication Critical patent/KR960005039B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/4805—Shape
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    • H—ELECTRICITY
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/491—Disposition
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체장치에서의 리드 프레임의 평면도, 제2도는 제1도의 B-B′선에 따른 단면도, 제3도는 제1도의 C-C′선에 따른 단면도, 제4도는 제1도에서의 다이 패드의 다른 실시예의 평면도, 제5도는 패키지의 두께를 설명하기 위한 단면 구조도 및 평면도.

Claims (3)

  1. 반도체소자(3)를 실장하는 수지밀봉형 반도체장치의 리드 프레임에 있어서, 복수개로 분할된 다이 패드(1)와, 상기 다이패드(1)상에 고착되어 상기 반도체소자 (3)와 그 다이패드(1)를 전기적으로 절연시키는 절연성 필름(15)을 구비한 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 복수의 다이 패드(1)의 내최저 2개는 당해 다이 패드 (1)를 지지하는 태브 리드가 패키지의 장변방향 및 단변방향중 어느쪽인가 한쪽 또는 양쪽으로 지지되는 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 복수의 다이 패드(1)는 당해 다이 패드를 지지하는 태브 리드가 1변 방향으로만 지지되는 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920000466A 1991-01-18 1992-01-15 수지밀봉형 반도체장치 KR960005039B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-004632 1991-01-18
JP3004632A JP2501953B2 (ja) 1991-01-18 1991-01-18 半導体装置

Publications (2)

Publication Number Publication Date
KR920015525A true KR920015525A (ko) 1992-08-27
KR960005039B1 KR960005039B1 (ko) 1996-04-18

Family

ID=11589391

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920000466A KR960005039B1 (ko) 1991-01-18 1992-01-15 수지밀봉형 반도체장치

Country Status (5)

Country Link
US (1) US5389817A (ko)
EP (1) EP0495474B1 (ko)
JP (1) JP2501953B2 (ko)
KR (1) KR960005039B1 (ko)
DE (1) DE69210423T2 (ko)

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TW276357B (ko) * 1993-03-22 1996-05-21 Motorola Inc
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame
TW299564B (ko) * 1995-10-04 1997-03-01 Ibm
JP3685585B2 (ja) * 1996-08-20 2005-08-17 三星電子株式会社 半導体のパッケージ構造
US5825628A (en) * 1996-10-03 1998-10-20 International Business Machines Corporation Electronic package with enhanced pad design
US6034423A (en) * 1998-04-02 2000-03-07 National Semiconductor Corporation Lead frame design for increased chip pinout
DE10205563B4 (de) * 2002-02-11 2009-06-10 Advanced Micro Devices, Inc., Sunnyvale Gehäustes Halbleiterbauelement mit zwei Die-Paddles sowie zugehöriges Herstellungsverfahren
US9349628B2 (en) * 2013-02-25 2016-05-24 Advanced Micro Devices, Inc. Method and an alignment plate for engaging a stiffener frame and a circuit board
US10566269B2 (en) * 2017-12-18 2020-02-18 Texas Instruments Incorporated Low stress integrated circuit package
US10361147B1 (en) 2018-06-28 2019-07-23 Ford Global Technologies, Llc Inverter power module lead frame with enhanced common source inductance

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4595945A (en) * 1983-10-21 1986-06-17 At&T Bell Laboratories Plastic package with lead frame crossunder
JPH06105721B2 (ja) * 1985-03-25 1994-12-21 日立超エル・エス・アイエンジニアリング株式会社 半導体装置
JPS62136056A (ja) * 1985-12-09 1987-06-19 Nec Corp リ−ドフレ−ム
JP2601838B2 (ja) * 1987-09-19 1997-04-16 株式会社日立製作所 樹脂封止型半導体装置及びその製造方法
KR880014671A (ko) * 1987-05-27 1988-12-24 미다 가쓰시게 수지로 충진된 반도체 장치
JPH01124244A (ja) * 1987-11-09 1989-05-17 Nec Corp リードフレーム
JP2706077B2 (ja) * 1988-02-12 1998-01-28 株式会社日立製作所 樹脂封止型半導体装置及びその製造方法
US4994895A (en) * 1988-07-11 1991-02-19 Fujitsu Limited Hybrid integrated circuit package structure
US5068708A (en) * 1989-10-02 1991-11-26 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
JPH0760837B2 (ja) * 1990-03-13 1995-06-28 株式会社東芝 樹脂封止型半導体装置
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions

Also Published As

Publication number Publication date
US5389817A (en) 1995-02-14
JPH04363031A (ja) 1992-12-15
DE69210423D1 (de) 1996-06-13
EP0495474A1 (en) 1992-07-22
EP0495474B1 (en) 1996-05-08
KR960005039B1 (ko) 1996-04-18
DE69210423T2 (de) 1996-10-10
JP2501953B2 (ja) 1996-05-29

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