KR920018849A - 반도체장치 및 그의 제조방법 - Google Patents

반도체장치 및 그의 제조방법 Download PDF

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Publication number
KR920018849A
KR920018849A KR1019920004356A KR920004356A KR920018849A KR 920018849 A KR920018849 A KR 920018849A KR 1019920004356 A KR1019920004356 A KR 1019920004356A KR 920004356 A KR920004356 A KR 920004356A KR 920018849 A KR920018849 A KR 920018849A
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insulating film
conductor
thin film
forming
film
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KR1019920004356A
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KR960016824B1 (ko
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모리요시 나까시마
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시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체장치 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 제1의 실시예에 있어 반도체장치의 구조를 표시하는 단면도.
제2도는 본 발명의 제2의 실시예에 있어 반도체장치의 구조를 표시하는 단면도.

Claims (3)

  1. 실리콘 기판과, 이 실리콘기판의 표면에, 제1절연막을 개재하여 형성된 도전체박막과, 이 도전체박막의 상면을 덮는 제2의 절연막과, 이 제2의 절연막상에 형성된 도전배선층을 구비하고, 상기 제2의 절연막에는 콘택트 홀이 설치되고, 이 콘택트홀을 통하여, 상기 도전체박막과 상기 도전체 배선층이 전기적으로 접속되어, 적어도 상기 콘택트홀직하의, 상기 도전체박막과 상기 실리콘기판과의 사이에, 선택적으로 절연제층, 또는 주위를 절연막으로 덮혀서 전기적으로 부유상태에 있는 도전체층을 형성한 반도체 장치.
  2. 실리콘 기판상에 층간절연용의 제1의 절연막을 형성하는 공정과, 상기 제1의 절연막상의 소정영역에, 선택적으로 도전체층을 형성하는 공정과, 상기 도전체층의 노출한 표면전선을 제2의 절연막으로 덮는 공정과, 상기 제1의 절연막상 및 상기 제2의 절연막상에, 도전체박막을 퇴적하는 공정과, 상기 도전체박막상에, 층간절연용의 제3의 절연막을 퇴적하는 공정과, 이 제3의 절연막의 상기 도전체층을 선택적으로 형성한 영역상의 위치에 상기 도전체박막표면의 일부가 노출하도록, 전위취출용의 콘택트홀을 여는 공정과, 상기 제3의 절연막상 및 상기 콘택트홀의 내부를 포함하는 영역에 도전체층을 형성하고, 이 도전체층을 상기 도전체박막과 전기적으로 접속되게 하는 공정을 구비한 반도체장치의 제조방법.
  3. 실리콘 기판상에 층간절연용의 제1의 절연막을 형성하는 공정과, 상기 제1의 절연막상의 소정영역에, 선택적으로 제2의 절연막을 형성하는 공정과, 상기, 제1의절연막상 및 상기 제2의 절연막상에, 도전체박막을 퇴적하는 공정과, 상기 도전체가막상에, 층간절연용의 제3의 절연막을 퇴적하는 공정과, 이 제3의 절연막의, 상기 제2의 절연막을 선택적으로 형성한 영역상의 위치에, 상기 도전체박막표면의 일부가 노출하도록, 전위취출용의 콘택트홀을 여는 공정과, 상기 제3의 절연막상 및 콘택트홀의 내부를 포함하는 영역에 도전배선층을 형성하고, 이 도전배선층을 상기 도전체박막과 전기적으로 접속되게 하는 공정을 구비한 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920004356A 1990-06-21 1992-03-17 반도체장치 및 그의 제조방법 KR960016824B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP16365590 1990-06-21
JP1990-163655 1990-06-21
JP1991-057545 1991-03-22
JP3057545A JPH04212426A (ja) 1990-06-21 1991-03-22 半導体装置およびその製造方法
JP91-057545 1991-03-22
JP91-163655 1991-06-21

Publications (2)

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KR920018849A true KR920018849A (ko) 1992-10-22
KR960016824B1 KR960016824B1 (ko) 1996-12-21

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US (1) US5229645A (ko)
JP (1) JPH04212426A (ko)
KR (1) KR960016824B1 (ko)
DE (1) DE4120592C2 (ko)

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JP3903189B2 (ja) * 1995-03-07 2007-04-11 マイクロン・テクノロジー・インコーポレーテッド Ｄｒａｍ半導体装置
US5903058A (en) * 1996-07-17 1999-05-11 Micron Technology, Inc. Conductive bumps on die for flip chip application
KR100255591B1 (ko) * 1997-03-06 2000-05-01 구본준 박막 트랜지스터 어레이의 배선 연결 구조 및 그 제조 방법
JP3397663B2 (ja) * 1997-03-19 2003-04-21 株式会社東芝 回路素子の製造方法
US6143649A (en) * 1998-02-05 2000-11-07 Micron Technology, Inc. Method for making semiconductor devices having gradual slope contacts
KR100443840B1 (ko) * 1998-09-01 2005-01-13 엘지.필립스 엘시디 주식회사 액정표시장치의제조방법
JP4021104B2 (ja) * 1999-08-05 2007-12-12 セイコーインスツル株式会社 バンプ電極を有する半導体装置
US6838769B1 (en) 1999-12-16 2005-01-04 Agere Systems Inc. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
GB2364170B (en) * 1999-12-16 2002-06-12 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same

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Also Published As

Publication number Publication date
JPH04212426A (ja) 1992-08-04
DE4120592C2 (de) 1996-03-28
KR960016824B1 (ko) 1996-12-21
DE4120592A1 (de) 1992-01-09
US5229645A (en) 1993-07-20

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