GB2364170B - Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same - Google Patents

Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same

Info

Publication number
GB2364170B
GB2364170B GB0030319A GB0030319A GB2364170B GB 2364170 B GB2364170 B GB 2364170B GB 0030319 A GB0030319 A GB 0030319A GB 0030319 A GB0030319 A GB 0030319A GB 2364170 B GB2364170 B GB 2364170B
Authority
GB
United Kingdom
Prior art keywords
bond pad
dual damascene
opening
pad
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0030319A
Other versions
GB2364170A (en
GB0030319D0 (en
Inventor
Sailesh Chittipeddi
William Thomas Cochran
Yehuda Smooha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/465,089 external-priority patent/US6838769B1/en
Priority claimed from US09/465,075 external-priority patent/US6417087B1/en
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of GB0030319D0 publication Critical patent/GB0030319D0/en
Publication of GB2364170A publication Critical patent/GB2364170A/en
Application granted granted Critical
Publication of GB2364170B publication Critical patent/GB2364170B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A dual damascene bond pad (27) resistant to stress effects within an integrated circuit is disclosed, allowing for the bond pad (27) to be formed over a substrate (1) containing active circuitry. The dual damascene structure is created by forming bond pad opening (20) and vias (19) in region (40), and depositing metal film (17) in the opening (20) and vias (19). The opening has barrier layer film (13) on bottom surface of opening (20) and vias (19) extending downwardly through barrier layer film (13) and lower dielectric film (11). A conductive layer (5) may be interposed between substrate region (1) and lower dielectric film (11). The reduction in stress of bond pad (27) results in the pad (27) being more resistant to cracking when an external wire (25) is attached to the pad (27), thus preventing leakage currents between the bond pad (27) and any underlying circuitry.
GB0030319A 1999-12-16 2000-12-12 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same Expired - Fee Related GB2364170B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/465,089 US6838769B1 (en) 1999-12-16 1999-12-16 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US09/465,075 US6417087B1 (en) 1999-12-16 1999-12-16 Process for forming a dual damascene bond pad structure over active circuitry

Publications (3)

Publication Number Publication Date
GB0030319D0 GB0030319D0 (en) 2001-01-24
GB2364170A GB2364170A (en) 2002-01-16
GB2364170B true GB2364170B (en) 2002-06-12

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GB0030319A Expired - Fee Related GB2364170B (en) 1999-12-16 2000-12-12 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same

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JP (1) JP4138232B2 (en)
KR (1) KR100691051B1 (en)
GB (1) GB2364170B (en)
TW (1) TW477000B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003068878A (en) * 2001-08-23 2003-03-07 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
DE10200932A1 (en) * 2002-01-12 2003-07-24 Philips Intellectual Property Discrete semiconductor device
US7096581B2 (en) * 2002-03-06 2006-08-29 Stmicroelectronics, Inc. Method for providing a redistribution metal layer in an integrated circuit
US6614091B1 (en) 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US7692315B2 (en) 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
JP2004095916A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
JP4528035B2 (en) * 2004-06-18 2010-08-18 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4674522B2 (en) * 2004-11-11 2011-04-20 株式会社デンソー Semiconductor device
WO2008015500A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improvements in chip manufacture and design
FR2959868A1 (en) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 SEMICONDUCTOR DEVICE HAVING CONNECTING PLATES WITH INSERTS
JP2013235127A (en) * 2012-05-09 2013-11-21 Seiko Epson Corp Electro-optic device, method for manufacturing electro-optic device and electronic apparatus
KR102437163B1 (en) 2015-08-07 2022-08-29 삼성전자주식회사 Semiconductor device
US10833119B2 (en) * 2015-10-26 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for front side illuminated image sensor
CN107845622B (en) * 2017-12-04 2022-04-08 长鑫存储技术有限公司 Chip stacked body with through-silicon via and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0224013A2 (en) * 1985-10-28 1987-06-03 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate
US5229645A (en) * 1990-06-21 1993-07-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
EP0926721A2 (en) * 1997-12-23 1999-06-30 Siemens Aktiengesellschaft Dual damascene with bond pads

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08293523A (en) * 1995-02-21 1996-11-05 Seiko Epson Corp Semiconductor device and its manufacture
JPH1041298A (en) * 1996-07-23 1998-02-13 Toshiba Corp Semiconductor device and its manufacture
JPH10261624A (en) * 1997-03-19 1998-09-29 Nec Corp Etching and multilayered interconnection structure
JP3647631B2 (en) * 1997-07-31 2005-05-18 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JPH11135506A (en) * 1997-10-31 1999-05-21 Nec Corp Manufacture of semiconductor device
JP3544464B2 (en) * 1997-11-26 2004-07-21 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP3382549B2 (en) * 1998-11-02 2003-03-04 キヤノン株式会社 Semiconductor device and active matrix substrate
JP2000299350A (en) * 1999-04-12 2000-10-24 Toshiba Corp Semiconductor device and its manufacture
JP2001196413A (en) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp Semiconductor device, method of manufacturing the same, cmp device and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0224013A2 (en) * 1985-10-28 1987-06-03 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate
US5229645A (en) * 1990-06-21 1993-07-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
EP0926721A2 (en) * 1997-12-23 1999-06-30 Siemens Aktiengesellschaft Dual damascene with bond pads

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JP4138232B2 (en) 2008-08-27
GB2364170A (en) 2002-01-16
KR100691051B1 (en) 2007-03-09
KR20010062445A (en) 2001-07-07
TW477000B (en) 2002-02-21
JP2001298029A (en) 2001-10-26
GB0030319D0 (en) 2001-01-24

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Effective date: 20161212