JP3382549B2 - Semiconductor device and active matrix substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an semiconductor device.
The present invention relates to a structure of an active matrix substrate, and particularly to a structure of a pad electrode portion of a semiconductor substrate.

[0002]

2. Description of the Related Art In a semiconductor substrate of a liquid crystal display device or a semiconductor device, a conventional damascene method using CMP for embedded wiring, especially a method for forming a bonding pad requiring a large area is disclosed in Japanese Patent Laid-Open No. 6-232121. The method described was taken. A typical drawing thereof is shown in FIG.

In FIG. 15, reference numeral 141 denotes a semiconductor substrate, 1
43 is an insulating film, 145 is a wiring pattern provided by removing the insulating film, 147 is an adhesion promoting layer, and 149a is a wiring or a bonding pad (pad electrode). An insulating film 143 is formed on the semiconductor substrate 141 on which a large number of field effect transistors are formed.

Next, the wiring pattern 1 is formed on the insulating film 143 by a known photolithography technique and etching technique.
A groove to be 45 is formed. Here, the width and length dimensions of the wiring pattern 145 are limited in order to prevent the concave shape of the wiring center portion due to dishing which is unavoidable in principle in the CMP process. In the case of Al, Cu and Al-based alloys, Cu-based alloys However, it is said that it is preferable to set the maximum to about 100 μm.

Next, an adhesion promoting layer 147 such as a TiN / Ti laminated film is formed, and then a wiring material 149a is formed, and C
The wiring material other than the embedded wiring and the adhesion promoting layer are removed by the MP method to form the wiring or the bonding pad 149a. 110 is a bonding wire when 149a is a bonding pad.

[0006]

However, in the above-mentioned conventional example, since the width and length of the embedded wiring are limited, the bonding pad 149a must be made small, and as a result, it is expensive for the wire bonding apparatus. The load on the device increases due to the need for accuracy. In the worst case, there is a drawback that the bonded wire 110 comes off the bonding pad 149a and the yield is reduced.

Further, even if the size of the wiring is limited, the concave shape in the central portion of the wiring cannot be eliminated in principle, and the bonding portion near the center of the bonding pad becomes thin, and as a result, the bonding wire is When pressed,
The thinned wiring portion is scooped out, and the bonding wire is pressed against the underlying insulating film. Since the bonding force between the bonding wire and the insulating film is small, the wire is very easily peeled off, and there is a drawback that the yield of wire bonding is reduced.

(Object of the Invention) An object of the present invention is to improve the yield of wire bonding by providing a large bonding pad without limiting the width and length of the embedded wiring.

Furthermore, the yield is improved by preventing the thinned wiring portion from being scooped by the concave shape of the central portion of the wiring and peeling off the bonded wire.

[0010]

SUMMARY OF THE INVENTION The present invention is an external device and an
Immediately below the connecting part between the connecting means for electrically connecting and the pad electrode
The wiring layer of the semiconductor device and the pad electrode
In a semiconductor device that contacts without being stored, the pad electrode is
A plurality of connection holes of different sizes that come into contact with the wiring layer are formed.
Characterized by being connected to the wiring layer
Is.

The present invention also provides a connection for electrically connecting to an external device.
Immediately below the connection between the connecting means and the pad electrode,
It is electrically connected to the formed semiconductor element to form a semiconductor electric circuit.
Any wiring and the pad conductive of wiring a plurality of layers constituting
In a semiconductor device in which the pole contacts without inclusions,
The pad electrode has a different size in contact with the arbitrary wiring.
Is connected to the arbitrary wiring by a plurality of connection holes
It is characterized by being present.

The present invention also provides a connection for electrically connecting to an external device.
Immediately below the connection between the connecting means and the pad electrode,
Switching element arranged for each pixel electrode having a surface
Arbitrary wiring among multiple layers for transmitting power or signals to
Of the wiring and the pad electrode are in contact with each other without inclusion.
In the active matrix substrate, the pad electrode is
For connecting multiple connection holes of different sizes that come into contact with any wiring.
Therefore, it is characterized in that it is connected to the arbitrary wiring.
It is something.

[Operation] According to the present invention, the thickness of the electrode in the wire bonding region is the sum of the thickness of the pad electrode and the thickness of the wiring electrode, and thus becomes substantially thick. As a result, a pad electrode having large vertical and horizontal dimensions and capable of strong bonding can be obtained. Hereinafter, the operation of the present invention will be further described.

According to the present invention, the pad electrode and the wiring layer of the semiconductor device are in direct contact with each other in the connection region between the lead-out wiring and the pad electrode without inclusion, that is, 1, the bonding wire (110) and the bonding pad (109)
Which is the wiring layer immediately below the bonding region (111) of
Since the Al (104) and the bonding pad (109) are bonded on the entire surface without sandwiching anything between them, the thickness of the electrode in the bonding region (111) is equal to that of the first Al (104) which is a wiring layer. Thickness + bonding pad (10
Since the thickness is 9), which is substantially larger, C
Even if a recess of several thousand Å is formed in the central portion of the bonding pad due to the dishing by MP, stable and strong bonding can be obtained.

Further, since a large-sized bonding pad (109) having a side of several hundreds of μm can be formed, a strong wire bonding can be obtained, the yield of the wire bonding process can be improved, and a low cost liquid crystal display device or the like can be obtained. Can be provided.

Further, according to the present invention, since the pad electrode and the wiring layer of the semiconductor device are connected by a plurality of connection holes, that is, as shown in FIG. 4, a large through hole is formed. By mixing (112) and small-sized through-holes (112 '), it is possible to obtain a low-resistance bonding pad and to achieve strong wire bonding at the same time, which results in a low-cost liquid crystal. A display device or the like can be provided.

Further, according to the present invention, in the pad electrode,
By disposing the polishing stopper made of a material different from that of the pad electrode, that is, by disposing the plasma SiO pillar (108 ') in the bonding pad (109) as shown in FIG. Since it functions as a stopper for the second Al (109-
The dishing of a) can be reduced. Therefore, the thickness of the Al electrode in the bonding region (111) is increased, and the reliability of wire bonding is further improved.

As described above, according to the present invention, since the pad electrode having a large thickness and a large area is provided, strong wire bonding can be performed and the yield of wire bonding is improved. As a result, it becomes possible to provide a low-cost liquid crystal display device.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (Reference Example) [Structure] FIG. 1 shows the structure of a bonding pad, which is a feature of this embodiment. In FIG. 1, (101) is a Si substrate, (1)
02) is a Si thermal oxide film formed by thermally oxidizing a Si substrate,
(103) is BPSG, (104) is the first Al that becomes the first wiring layer, and (105) is plasma S that is an interlayer insulating film.
iO, (106) a light-shielding layer made of a metal material such as Ti, W, (107) plasma SiN, (108) plasma SiO, (109) bonding pad (pad electrode), (110) bonding wire ( (111) is a bonding wire (11)
0) is a bonding region bonded to the bonding pad (109).

The feature of this embodiment is that the first Al (10) is a wiring layer immediately below the bonding region (111) between the bonding wire (110) and the bonding pad (109).
4) and the bonding pad (109) are joined together on the entire surface without inclusions between them, and the thickness of the electrode in the bonding region (111) is the first Al ( 104) thickness + bonding pad (10
The thickness is 9), which is a substantial increase.

As a result, even if a recess of several thousand Å is formed in the central portion of the bonding pad due to dishing by CMP, stable and strong bonding can be obtained.

Further, since a large-sized bonding pad (109) having a side of several hundreds μm can be formed, strong wire bonding can be obtained, the yield of the wire bonding process is improved, and a low-cost liquid crystal display device is obtained. Can be provided.

[Manufacturing Method] Next, a method of forming the bonding pad of this embodiment will be described with reference to FIGS. 2 (a) to 2 (d).

First, as shown in FIG. 2A, in the step of forming the semiconductor element described above, the Si substrate (101) is thermally oxidized to form a Si thermal oxide film (10) which is a field oxide film.
2) is formed about 8000Å. Next, BPSG (103)
To form about 7,000 Å. At this time, if necessary, p
The gate electrode material such as ollySi or W silicide is Si
It can be formed between the thermal oxide film (102) and the BPSG (103) immediately below the region where the bonding pad is formed.

The first Al (104) is Ti 20 from the lower layer.
0Å / TiN 1000Å / AlSiW 5000Å /
It has a laminated structure of TiN300Å and is patterned by known lithography and etching techniques. The dimensions of the first Al (104) are 90 μm in width and 290 in length.
μm. In the present embodiment, the first Al (10
Although the example in which 4) is patterned is shown, it is also possible to form it by a damascene method using CMP.

Next, plasma SiO (105) is formed. Here, the plasma SiO (105) is flattened by a method such as SOG etchback and interlayer film CMP. The flattening is advantageous in terms of easiness of patterning in the next step and the yield corresponding to the patterning, but it is not always essential, and the presence or absence of the flattening can be selected as necessary.

Next, a light-shielding layer (106) is formed with a thickness of about 3000Å. The material of the light shielding layer (106) is, as described above,
High melting point metals such as Ti, TiN, W and Mo are preferable in terms of material stability. The patterning of the light-shielding layer (106) is performed so that the incident light does not reach the Si substrate.
4) Patterning is performed so that an overlapping portion is formed. Here, the overlap of each of the four sides was 10 μm. Then, plasma SiN (107) is deposited on the entire surface by about 4000Å.

Next, as shown in FIG. 2B, plasma SiO (108) is formed into a desired bonding pad shape after forming a film of about 10,000 Å. Here, the width is 100 μm and the length is 300 μm. In the liquid crystal display device, this step is performed together with the step of forming the groove of the reflective electrode. During etching, the plasma SiN (107) functions as an etching stopper.

Next, as shown in FIG. 2C, the first Al
A through hole (112) for forming a bond between (104) and the bonding pad is formed. Normally, a plurality of through holes (112) having a size of several μm □ are formed in the bonding pad portion.
One through hole having a size of μm and a length of 260 μm is formed.

In FIG. 2D, the second Al (109-
About 18000Å is deposited. Second Al (109-
Since a) is formed in the same process as the above-mentioned reflective electrode,
A high reflectance material such as Al, Pt, or Ag is suitable, and pure Al is used here to improve the embedding property.
A film was formed by sputtering under the conditions of a vacuum degree of 10 ⁻⁸ torr or less and a wafer temperature of 430 ° C.

Subsequently, the second Al (109-a) on the plasma SiO (108) is removed by CMP to obtain the structure of FIG. The CMP conditions were EPO-114 manufactured by EBARA CORPORATION for the CMP apparatus, Supreme RN-H manufactured by Rodel Nitta for the polishing cloth, and PLANERLITE-5 manufactured by Fujimi Incorporated for the slurry.
102, a load of 300 gf / cm ² , a wafer carrier rotation speed of 30 rpm, and a turntable rotation speed of 31 rpm, and the average polishing rate of Al at this time is about 2200 Å /
min, and the dishing amount of the bonding pad (109) was about 5000Å.

FIG. 3 shows Al when polished under the above CMP conditions.
It is a correlation diagram of the dimension of an electrode and dishing by CMP. It can be seen that the dishing amount increases as the Al dimension increases.

The dimensions of the bonding pads and the like mentioned here are merely examples, and the number is not limited to this, and the number of through holes (112) is not limited to one, and a plurality of holes may be provided. It goes without saying that it is also possible.

Further, although the example of the two-layer wiring is given in this embodiment, the present invention can be applied to the multi-layer wiring of three layers or more.

Furthermore, in the present embodiment, an example of wire bonding is given as the connecting means, but the bonding pad of this structure has an anisotropic conductive film, a solder bump, a silver paste, a leaf spring as another connecting means. It can also be applied to such methods. The above application is also applied to the following embodiments. It is needless to say that the present embodiment and the subsequent embodiments are not limited to the pad electrode structure of the active matrix substrate, but are also useful as pad electrodes of semiconductor devices such as CPU and DRAM.

[0036] The first embodiment A first embodiment of the present invention will be described with reference to manufacturing process diagrams of FIGS. 4 (a) ~ FIG 4 (c). In FIG. 4A, the steps up to the formation of the plasma SiO (108) are the same as those in the reference example .

As shown in FIG. 4A, when forming a through hole, one or a plurality of through holes (112) having a size of several tens to several hundreds of μm and a through hole of several μm □ ( 112 ') are provided in plurality.

In addition, the same method as in the first embodiment is applied to the second A
1 (109-a) is formed into a film (FIG. 4-b), and plasma SiO (108) is also formed by CMP under the same conditions as in the first embodiment.
The upper second Al (109-a) is removed to obtain the bonding pad structure shown in FIG.

The feature of this embodiment is that one side is several tens to several hundreds μm.
In addition to the through hole (112), one or more through holes (112 ′) of several μm □ are provided. In the liquid crystal display device, the through hole (112 ′) of several μm □ has the same size as or a size close to that of the reflective electrode section, and the through hole of the reflective electrode section and the through hole of several μm □ of the bonding pad section. The etching rates for etching when forming holes are almost equal. On the other hand, the etching rate of a large-sized through hole (112 ′) having a side of several tens to several hundreds of μm is the above-mentioned through hole (112 ′) of several μm □.
Phenomenon smaller than that (micro loading effect)
Therefore, when the etching time is set to a through hole of several μm □, the etching of the large-sized through hole (112) is under-etching, so that only the large-sized through hole (112) has the first Al ( The bonding resistance between the bonding pad 104 and the bonding pad 109 may increase.

Therefore, in this embodiment, the large-sized through hole (112) and the small-sized through hole (11) are used.
By mixing 2 '), electrical connection can be surely realized by a small-sized through hole (112'), so that a low resistance bonding pad can be obtained and strong wire bonding can be achieved at the same time. It will be possible. This makes it possible to provide a low-cost liquid crystal display device.

[0041] The second embodiment A second embodiment of the present invention will be described with reference to FIG. 5 (a) ~ FIG 5 (b) and 6.

In FIG. 5A, plasma SiO (1
08) is the same as the reference example and the first embodiment.

As shown in FIG. 5A, plasma SiO
When patterning (108), plasma SiO pillars (108 ') that function as CMP stoppers are formed. In this embodiment, the plasma SiO column (10
The cross-sectional shape of 8 ') was square and the dimension was 10 μm on each side. The cross-sectional shape, dimensions, and number are not limited to those set here, and can be set arbitrarily.

Next, as shown in FIG. 5B, a through hole (112) is formed. Although a plurality of through holes (112) having a plurality of dimensions are formed here, it goes without saying that a single through hole can be formed as in the first embodiment.

Next, as shown in FIG. 5C, the second Al
After depositing (109-a), the film is polished under the same CMP conditions as in the first embodiment to obtain the bonding pad structure of FIG. FIG. 6 is a perspective view of FIG.

The feature of this embodiment is that the plasma SiO column (108 ') is arranged in the bonding pad (109). Since the column functions as a stopper for CMP, the dishing of the second Al (109-a) is performed. Can be made smaller. Therefore, the bonding area (1
The thickness of the Al electrode in 11) is increased, and the reliability of wire bonding is further improved.

( Third Embodiment) A liquid crystal display device to which the bonding pad of the present invention is applied will be described below. The bonding pad structure of the present invention is applied to the electrode pad 352 of FIG. 11 described later.

Although the embodiments of the present invention are described with reference to a plurality of liquid crystal panels, the invention is not limited to the respective embodiments. It goes without saying that the effect is increased by combining the technologies of the mutual forms. Further, the structure of the liquid crystal panel is described using a semiconductor substrate, but the structure is not necessarily limited to the semiconductor substrate.
The structure described below may be formed on an ordinary transparent substrate. The liquid crystal panels described below are all MO
Although it is an SFET or TFT type, it may be a two-terminal type such as a diode type. Furthermore, the liquid crystal panels described below are not only for home TVs, but also for projectors, head-mounted displays, 3D video game devices, laptop computers, electronic organizers, video conferencing systems,
It is effective as a display device for car navigation and airplane panels.

FIG. 7 shows a cross section of the liquid crystal panel portion of the present invention. In FIG. 7, 301 is a semiconductor substrate, and 302 and 30.
2'denotes p-type and n-type wells, 303 and 303 ', respectively.
Is a source region of the transistor, 304 is a gate region, 3
Reference numerals 05 and 305 'are drain regions.

As shown in FIG. 7, since a high breakdown voltage of 20 to 35 V is applied to the transistor in the display region, the source and drain layers are not formed in a self-aligned manner with respect to the gate 304, and an offset is applied. , a source region 303 therebetween ', the drain region 305' as shown in a low concentration in the p-well n ^- layer of low concentration in the n-well p ^- layer is provided. By the way, the offset amount is 0.5-2.0 μm
Is preferred. On the other hand, although a part of the peripheral circuit is shown on the left side of FIG. 7, in the part of the peripheral circuit, the source and drain layers are formed in self-alignment with the gate.

Here, the offset of the source and drain has been described, but it is effective to change the offset amount according to each withstand voltage and optimize the gate length in addition to the presence or absence of them. This is because a part of the peripheral circuit is a logic circuit, and this part is generally 1.5 to 5V.
Since the system drive is sufficient, the self-alignment structure is provided in order to reduce the transistor size and improve the transistor driving force. The substrate 301 is made of a p-type semiconductor,
The substrate has the lowest potential (usually the ground potential), and the n-type well receives the voltage applied to the pixel, that is, 20 to 35 V in the case of the display region, while the logic part of the peripheral circuit has the logic drive voltage 1 0.5 to 5V is applied. With this structure, it is possible to configure an optimum device according to each voltage, and it is possible not only to reduce the chip size but also to realize high pixel display by improving the driving speed.

In FIG. 7, 306 is a field oxide film, 310 is a source electrode connected to the data wiring, and 3 is a source electrode.
Reference numeral 11 is a drain electrode connected to the pixel electrode, 312 is a pixel electrode which also serves as a reflecting mirror, 307 is a light-shielding layer covering the display region and the peripheral region, and Ti, TiN, W, Mo and the like are suitable.

As shown in FIG. 7, the light shielding layer 307 is
In the display area, the pixel electrode 312 and the drain electrode 311 are covered except for the connection portion, but in the peripheral pixel area,
The light shielding layer 307 is not arranged in a region where the wiring capacity is heavy, such as a part of the video line and the clock line, and high-speed signals can be transferred. When the light of the illumination light is mixed in the portion where the light shielding layer 307 is removed to cause a malfunction of the circuit, the device for covering the region where the light shielding layer 307 is not arranged in the layer of the pixel electrode 312 is devised.

Reference numeral 308 denotes an insulating layer below the light shielding layer 307,
The P-SiO layer 318 is flattened by SOG, and the P-SiO layer 318 is further flattened.
It was covered with 08 to ensure the stability of the insulating layer 308. S
In addition to flattening by OG, P-TEOS (Phosph
It is needless to say that a method of forming an o-Tetraetoxy-Silane) film, covering the P-SiO layer 318, and then subjecting the insulating layer 308 to CMP treatment for planarization may be used.

Reference numeral 309 denotes a reflective electrode (pixel electrode) 31.
2 is an insulating layer provided between the light shielding layer 307 and the light shielding layer 307, and serves as a charge storage capacity of the reflective electrode (pixel electrode) 312 via the insulating layer 309. SiO ₂ for large capacity formation
Addition to, P-SiN of high dielectric constant, Ta ₂ O _5, and SiO ₂
A laminated film with is effective. Ti, Ti on the light shielding layer 307
5 by installing on a flat metal such as N, Mo, W
A film thickness of about 00 to 5000 angstrom is suitable.

Further, 314 is a liquid crystal material, 315 is a common transparent electrode, 316 is a counter substrate, 317 and 317 'are high-concentration impurity regions, 319 is a display region, and 320 is an antireflection film.

As shown in FIG. 7, high-concentration impurity layers 317 and 317 'having the same polarity as the wells 302 and 302' formed in the lower portion of the transistor are formed in the peripheral portion and the contents of the wells 302 and 302 '. Even when a high-amplitude signal is applied to the source, the well potential is fixed at a desired potential in the low resistance layer, and thus stable and high-quality image display can be realized. Further, the high-concentration impurity layers 317 and 317 'are provided between the n-type well 302' and the p-type well 302 via a field oxide film, which is directly under the field oxide film used in a normal MOS transistor. No channel stop layer is required.

These high-concentration impurity layers 317 and 317 '
Can be done simultaneously in the source and drain layer formation process, so the number of masks and man-hours in the manufacturing process can be reduced.
Cost reduction was achieved.

Next, reference numeral 313 is an antireflection film provided between the common transparent electrode 315 and the counter substrate 316, and is constructed so that the interface reflectance is reduced in consideration of the refractive index of the liquid crystal at the interface. To be done. In that case, an insulating film having a smaller refractive index than the counter substrate 316 and the transmissive electrode 315 is preferable.

Next, a plan view of the present invention is shown in FIG. Figure 8
, 321 is a horizontal shift register, 322 is a vertical shift register, 323 is an n-channel MOSFET,
324 is a p-channel MOSFET, 325 is a storage capacitor, 326 is a liquid crystal layer, 327 is a signal transfer switch, 32
Reference numeral 8 is a reset switch, 329 is a reset pulse input terminal, 330 is a reset power supply terminal, and 331 is a video signal input terminal. Although the semiconductor substrate 301 is p-type in FIG. 7, it may be n-type.

The well region 302 'is formed on the semiconductor substrate 301.
To the opposite conductivity type. Therefore, in FIG. 7, the well region 302 is p-type. p-type well region 302
It is desirable that the n-type well region 302 ′ and the n-type well region 302 ′ be implanted with impurities at a higher concentration than the semiconductor substrate 301.
The impurity concentration of the semiconductor substrate 301 is 10 ¹⁴ to 10 ¹⁵ (cm
^-3 ), the concentration of disordered substances in the well region 302 is 10 ¹⁵ to
10 ¹⁷ (cm ⁻³ ) is desirable.

The source electrode 310 is a data line to which a display signal is sent, and the drain electrode 311 is a pixel electrode 3.
Connect to 12. These electrodes 310 and 311 are usually formed of Al, AlSi, AlSiCu, AlGeCu, Al.
Cu wiring is used. When a via metal layer made of Ti and TiN is used for the contact surface between the lower part of these electrodes 310 and 311 and the semiconductor, stable contact can be realized. Further, contact resistance can be reduced. The pixel electrode 312 has a flat surface and is preferably made of a high-reflecting material, and is a normal wiring metal such as Al, AlSi, AlSiCu, AlGeCu, A.
Besides lCu, it is possible to use materials such as Cr, Au, and Ag. Further, in order to improve the flatness, the surfaces of the base insulating layer 309 and the pixel electrode 312 are processed by the chemical mechanical polishing (CMP) method.

The storage capacitor 325 is a capacitor for holding a signal between the pixel electrode 312 and the common transparent electrode 315. A substrate potential is applied to the well region 302. In this embodiment, the transmission gate configuration of each row is
In the first row from the top, the top is the n-channel MOSFET 323.
Then, the lower row is the p-channel MOSFET 324, the second row is the p-channel MOSFET 324, and the lower row is the n-channel MOSFET 323. As described above, not only is the striped well in contact with the power supply line around the display region, but a thin power supply line is also provided in the display region for contact.

At this time, stabilization of the well resistance is key. Therefore, in the case of a p-type substrate, a structure is adopted in which the contact area or the number of contacts inside the display region of the n-well is increased more than that of the p-well. Since the p-well has a constant potential on the p-type substrate, the substrate plays a role as a low resistance body. Therefore, the influence of the fluctuation of the signal input / output to / from the source and drain of the island-shaped n-well is likely to be large, but this can be prevented by increasing the contact from the upper wiring layer. As a result, stable and high-quality display was realized.

A video signal (video signal, pulse-modulated digital signal, etc.) is input from the video signal input terminal 331, the signal transfer switch 327 is opened / closed according to the pulse from the horizontal shift register 321, and each data wiring is connected. Output. From the vertical shift register 322, a high pulse is applied to the gate of the n-channel MOSFET 323 and a low pulse is applied to the gate of the p-channel MOSFET in the selected row.

As described above, the switch of the pixel portion is composed of a single crystal CMOS transmission gate, and the signal written to the pixel electrode does not depend on the threshold value of the MOSFET, and the source signal can be written completely. Have advantages.

Further, since the switch is composed of a single crystal transistor, there is no unstable behavior at the crystal grain boundaries of the polysi-TFT, and a highly reliable and high speed drive without variation can be realized.

Next, regarding the configuration of the panel peripheral circuit, FIG.
Will be explained. In FIG. 9, 337 is a liquid crystal display area, 332 is a level shifter circuit, 333 is a video signal sampling switch, 334 is a horizontal shift register, 335 is a video signal input terminal, and 336 is a vertical shift register.

With the above-described structure, the logic circuit such as the shift register for both H and V has the video signal input terminal 3
Since the amplitude of about 25V, 30V is supplied from 35,
It can be driven at an extremely low value of about 1.5 to 5 V, and high speed and low power consumption can be achieved. Horizontal and vertical SR here is
The scanning direction is bidirectional with a selection switch, and it is possible to respond to changes in the layout of the optical system without changing the panel, and the same panel can be used for different product series, reducing cost. There is a merit that can be achieved.

In FIG. 9, the video signal sampling switch has a one-polarity one-transistor configuration, but the present invention is not limited to this, and a CMOS transmission gate configuration is used to convert all input video lines into signal lines. It goes without saying that you can write.

In addition, when the CMOS transmission gate structure is adopted, there is a problem that the video signal is fluctuated due to the difference in the area of the NMOS gate and the PMOS gate and the overlapping capacitance of the gate and the source / drain. To prevent this, by connecting the source and drain of the MOSFET having a gate amount of about ½ of that of the MOSFET of each polarity sampling switch to the signal line and applying a reverse-phase pulse, the swing can be prevented. , A very good video signal was written on the signal line. This has made it possible to display even higher quality.

Next, the direction in which the video signal and the sampling pulse are accurately synchronized will be described with reference to FIG. For this purpose, it is necessary to change the delay amount of the sampling pulse. 342 is a pulse delay inverter, 343 is a switch for deciding which delay inverter to select, 344 is an output whose delay amount is controlled, 345 is a capacitor (outB is a reverse phase output, o
ut is an in-phase output). Reference numeral 346 is a protection circuit.

From SEL1 (SEL1B) to SEL3 (S
Depending on the combination of EL3B), the number of delay inverters 342 to be passed can be selected.

By incorporating this synchronizing circuit in the panel, the delay amount of the pulse from the outside of the panel is
R. G. In the case of the B3 plate panel, even if the symmetry is broken due to the jig or the like, it can be adjusted with the above selection switch. G. B
A good display image was obtained with no displacement due to the high pulse phase region of. Further, it goes without saying that it is also effective to incorporate a temperature measuring diode inside the panel and refer to the delay amount from the table by the output thereof to correct the temperature.

Next, the relationship with the liquid crystal material will be described.
In FIG. 7, a flat counter substrate structure is shown, but the common electrode substrate 316 is formed with irregularities in order to prevent interface reflection of the common transparent electrode 315, and the common transparent electrode 315 is formed on the surface thereof.
Is provided. Further, an antireflection film 320 is provided on the opposite side of the common electrode substrate 316. In order to form these irregularities, a method of sand-polishing with fine abrasive grains is also effective for high contrast.

Polymer network liquid crystal PNLC was used as the liquid crystal material. However, PDLC or the like may be used as the polymer network liquid crystal. The polymer network liquid crystal PNLC is produced by a polymerization phase separation method. A liquid crystal and a polymerizable monomer or oligomer are used to form a solution, which is then injected into a cell by a usual method, and then the liquid crystal and the polymer are phase-separated by UV polymerization to form a polymer in the liquid crystal network. PNLC has many liquid crystals (70-9
0 wt%).

In PNLC, anisotropy of refractive index (Δ
Light scattering is not strong when a nematic liquid crystal having a high n) is used, and driving can be performed at a low voltage when a nematic liquid crystal having a large dielectric anisotropy (Δε) is used. The size of the polymer network, that is, the distance between the centers of the meshes is 1 to 1.5
At (μm), the light scattering is strong enough to obtain high contrast.

Next, the relationship between the seal structure and the panel structure will be described with reference to FIG. In FIG.
Reference numeral 351 is a seal portion, 352 is an electrode pad, and 353 is a clock buffer circuit. The amplifier section (not shown) is used as an output amplifier at the panel electrical inspection.
Further, there is an Ag paste portion (not shown) for taking the potential of the counter substrate, and 356 is a display portion made of a liquid crystal element, and 357 is a peripheral circuit portion such as a horizontal / vertical shift register (SR). The seal portion 351 is contacted with a pressure-bonding material or an adhesive for bonding a semiconductor substrate (301 in FIG. 7) provided with pixel electrodes 312 around four sides of the display portion 356 and a glass substrate having a common electrode 315. Showing the area, the sealing portion 35
After bonding with 1, the liquid crystal is sealed in the display portion 356 and the shift register portion 357.

As shown in FIG. 11, in the present embodiment, both the inside and outside of the seal have the total chip si.
The circuit is provided so that ze becomes small. In the present embodiment, the pad drawers are concentrated on one side of the panel, but it is possible to take out from both sides of the long side and from multiple sides instead of one side, and handle a high-speed clock. Sometimes effective.

Further, since the panel of the present invention uses the semiconductor substrate such as the Si substrate, when the substrate is irradiated with strong light like the projector and the side wall of the substrate is also exposed to the light, the substrate potential changes, It may cause malfunction of the panel. Therefore, the side wall of the panel and the peripheral circuit portion of the display area on the upper surface of the panel serve as a substrate holder that can shield light, and the back surface of the Si substrate has a high thermal conductivity via an adhesive having a high thermal conductivity. It has a holder structure in which a metal such as Cu is connected.

Next, the structure of the reflective electrode and the manufacturing method thereof will be described. The completely flattened reflective electrode structure of the present invention is different from the usual method of patterning a metal and then polishing the same, in advance, a groove is etched at the electrode pattern, and a metal film is formed there. This is a new method in which the metal on the region where the electrode pattern is not formed is removed by polishing and the metal on the electrode pattern is flattened. Moreover, the width of the wiring is much wider than the area other than the wiring, and the common problems of the conventional etching apparatus cause the following problems, and the structure of the present invention cannot be manufactured. That is, when etching is performed, a polymer is deposited during the etching and patterning cannot be performed.

Therefore, oxide film type etching (CF ₄ / C
HF ₃ system), the conditions were changed. In FIG. 12, (a) shows the conventional total pressure at 1.7 torr, and (b) shows the current 1.0 torr.

When the deposition gas CHF ₃ is reduced under the condition of FIG. 12A, the polymer deposition is surely reduced, but the difference in size between the pattern close to the resist and the pattern far from the resist (loading effect). It can be seen that is extremely large and cannot be used.

In FIG. 12 (b), in order to suppress the loading effect, the pressure is gradually reduced, and when the pressure is 1 torr or less, the loading effect is considerably suppressed and the CHF is reduced.
It was found that ₃ was set to zero and etching with CF ₄ alone was effective.

Further, almost no resist is present in the pixel electrode region, and the peripheral portion is occupied by the resist.
It was found that it is difficult to form a structure, and it is effective to provide an empty electrode equivalent to a pixel electrode and its shape up to the peripheral portion of the display area.

By adopting this structure, the step between the display section and the peripheral section or the seal section, which has been conventionally used, is eliminated, the gap accuracy is improved, the in-plane uniform pressure is increased, and the unevenness at the time of injection is also reduced. The effect that high-quality image quality can be improved with high yield was obtained.

Next, an optical system incorporating the reflection type liquid crystal panel of the present invention will be described with reference to FIG. Figure 1
3, 371 is a light source such as a halogen lamp, 372
Is a condenser lens for narrowing down the light source image, 373 and 375 are planar convex Fresnel lenses, and 374 is R.I. G. It is a color separation optical element that decomposes into B, and a dichroic mirror, a diffraction grating, etc. are effective.

376 is an R.I. G. Each of the lights separated into the B light is converted into R. G. The respective mirrors 377 leading to the B3 panel are field lenses for illuminating the condensed beam to the reflection type liquid crystal panel by parallel light, and the reference numeral 378 is limited to the position of the reflection type liquid crystal element 379 described above. Further, reference numeral 380 denotes a projection lens which combines and enlarges a plurality of lenses, and 38
Reference numeral 1 denotes a screen, which is usually composed of two plates, a Fresnel lens for converting the projection light into parallel light and a lenticular lens for displaying a wide viewing angle vertically and horizontally, so that a clear and high-contrast bright image can be obtained. .

In the configuration of FIG. 13, only one color panel is shown, but the color separation optical element 374 to the squeezed portion 37 are shown.
The areas 9 are separated into three colors, and three panel panels are arranged. Further, it is needless to say that by providing a microlens array on the surface of the reflective liquid crystal device panel and irradiating different pixel regions with different incident light, not only three plates but also a single plate structure can be used. A voltage is applied to the liquid crystal layer of the liquid crystal element, and the light specularly reflected by each pixel passes through the narrowed portion 379 and is projected on the screen.

On the other hand, when a voltage is not applied and the liquid crystal layer is a scatterer, the light incident on the reflection type liquid crystal element is isotropically scattered, and the angle at which the aperture of the diaphragm portion 379 is seen. Other than the scattered light inside, it does not enter the projection lens. This displays black. As can be seen from the above optical system, since a polarizing plate is not necessary and the signal light enters the projection lens with high reflectance over the entire surface of the pixel electrode, a display that is 2-3 times brighter than the conventional display can be realized. As described in the above embodiments, antireflection measures are applied to the surface and interface of the counter substrate,
The noise light component was extremely small, and high contrast display was realized. Further, since the panel size can be made small, all the optical elements (lenses, mirrors etc.) are made compact, and low cost and light weight are achieved.

The color unevenness, the brightness unevenness, and the fluctuation of the light source can be corrected by inserting an integrator (a fly-eye lens type rod type) between the light source and the optical system. Was solved.

Peripheral electric circuits other than the liquid crystal panel will be described with reference to FIG. In FIG. 14, 385
Is a power supply and is mainly separated into a lamp power supply and a panel or signal processing circuit driving system power supply. 386 is a plug, 38
A lamp temperature detector 7 controls the control board 388 to stop the lamp if the lamp temperature is abnormal. This is controlled not only by the lamp but also by the 389 filter safety switch. For example, if an attempt is made to open the high temperature lamp house box, safety measures are taken to prevent the box from opening. 39
0 is a speaker, 391 is a voice board, and a processor for 3D sound, surround sound, etc. can be built in if required. An expansion board 392 includes an S terminal for a video signal, an input terminal for an external device 396 for video signal composite video, audio, etc., a selection switch 395 for selecting which signal to select, and a tuner 394.
A signal is sent to the expansion board 2 via 93. On the other hand, the expansion board 2 mainly has a video from another series and a Dsub15 pin terminal of a computer, and via the switch 450 for switching the video signal from the decoder 393,
It is converted into a digital signal by the A / D converter 451.

Reference numeral 453 is a main board mainly composed of a memory such as a video RAM and a CPU. The NTSC signal A / D converted by the A / D converter 451 is once stored in the memory and is allocated to a high pixel number,
The signal processing is performed by interpolating a signal of lack of empty elements that does not match the number of liquid crystal elements, and performs signal processing such as γ conversion edge gradation and bright adjustment bias adjustment suitable for liquid crystal display elements. If not only the NTSC signal but also the computer signal, for example, the VGA signal, in the case of the high resolution XGA panel, the resolution conversion processing is also performed. The main board 453 performs not only one image data but also processing such as synthesizing a computer signal with NTSC signals of a plurality of image data. The output of the main board 453 is converted from serial to parallel, and is supplied to the head board 454 in a form that is less susceptible to noise. This headboard 454 again performs parallel / serial conversion, D / A conversion, and division according to the number of video lines on the panel, and via the drive amplifier,
B. G. A signal is written in the R color liquid crystal panels 455, 456, 457. Reference numeral 452 is a remote control operation panel, and the computer screen can be easily operated in the same manner as a TV. Further, each of the liquid crystal panels 455, 456, 457 has the same liquid crystal device configuration provided with a color filter of each color, and the horizontal / vertical scanning circuit to which the one described in the above embodiment is applied. As described above, in each liquid crystal device, an image that does not necessarily have a high resolution is processed into a high-quality image by processing, so that the display result of the present invention can display an extremely beautiful image.

[0094]

According to the present invention, since the pad electrode and the wiring layer of the semiconductor device are directly in contact with each other in the connection region between the lead wire and the pad electrode without inclusions, bonding is performed. The thickness of the electrode in the region is the thickness of the wiring layer + the thickness of the bonding pad, which is substantially large, so even if a recess of several thousand Å occurs in the center of the bonding pad due to dishing by CMP. Stable and strong bonding can be obtained.

Further, since a large-sized bonding pad having a side of several hundreds of μm can be formed, strong wire bonding can be obtained, the yield of the wire bonding process is improved, and a low cost liquid crystal display device or the like is provided. be able to.

Further, according to the present invention, since the pad electrode and the wiring layer of the semiconductor device are connected to each other through a plurality of connection holes having a plurality of sizes, a reliable electrical connection can be realized. It is possible to obtain a bonding pad having a low resistance and also to achieve strong wire bonding at the same time, which makes it possible to provide a low-cost liquid crystal display device or the like.

Further, according to the present invention, in the pad electrode,
By disposing the polishing stopper made of a material different from that of the pad electrode, dishing of the pad electrode can be reduced. Therefore, the thickness of the pad electrode in the bonding region is increased, and the reliability of wire bonding is further improved.

As described above, according to the present invention, since the pad electrode having a large thickness and a large area is provided, strong wire bonding is possible and the yield of wire bonding is improved. As a result, it becomes possible to provide a low-cost liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a reference example .

FIG. 2 is a cross-sectional view showing a manufacturing process of a reference example .

FIG. 3 is a correlation diagram of Al wiring width and Al dishing amount.

FIG. 4 is a cross-sectional view showing a manufacturing process of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 6 is a perspective view of a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a liquid crystal device manufactured by CMP according to the present invention.

FIG. 8 is a schematic circuit diagram of a liquid crystal device according to the present invention.

FIG. 9 is a block diagram of a liquid crystal device according to the present invention.

FIG. 10 is a circuit diagram including a delay circuit of an input unit of the liquid crystal device according to the present invention.

FIG. 11 is a conceptual diagram of a liquid crystal panel of a liquid crystal device according to the present invention.

FIG. 12 is a graph for judging the quality of the etching process in manufacturing the liquid crystal device according to the present invention.

FIG. 13 is a conceptual diagram of a liquid crystal projector using a liquid crystal device according to the present invention.

FIG. 14 is a circuit block diagram showing the inside of a liquid crystal projector according to the present invention.

FIG. 15 is a cross-sectional view showing a conventional electrode structure.

[Explanation of symbols]

101 Si substrate 102 Si thermal oxide film 103 BPSG 104 1st Al 105 plasma SiO 106 light shielding layer 107 Plasma SiN 108 plasma SiO 108 'Plasma SiO support 109 bonding pad 109-a Second Al 110 bonding wire 111 Bonding area 112 through hole 112 'through hole 141 semiconductor substrate 143 insulating film 145 wiring pattern 147 adhesion promoting layer 149a wiring 301 Semiconductor substrate 302,302 'p-type and n-type wells 303, 303 ', 303 "Source area 304 gate area 305, 305 ', 305 "drain region 306 LOCOS insulation layer 307 Light-shielding layer 308 PSG 309 Plasma SiN 310 Source electrode 311 Connection electrode 312 Reflective electrode & pixel electrode 314 Liquid crystal layer 315 Common transparent electrode 316 Counter electrode 317, 317 'High concentration impurity region 319 display area 320 Antireflection film 321 and 322 shift registers 332 Boost level shifter 342 inverter 351 seal 378 liquid crystal device 455, 456, 457 liquid crystal device

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/768 H01L 21/3213 H01L 21/60 G09F 9/30 338 G02F 1/1345

Claims (6)

(57) [Claims] 1. Connection means for electrically connecting to an external device
Immediately below the connection portion with the pad electrode, the wiring layer of the semiconductor device and
For semiconductor devices in which pad electrodes are in contact without inclusions
The pad electrodes have different sizes in contact with the wiring layer.
Be connected to the wiring layer by a plurality of connection holes
A semiconductor device characterized by: To wherein in the pad electrode, the semiconductor device according to claim 1, characterized in that it arranged a polishing stopper consisting <br/> different material as the pad electrode. 3. A connecting means and a pad for electrically connecting with an external device.
Just below the connection with the electrode
A plurality of elements that are electrically connected to body elements to form a semiconductor electric circuit
Any wiring of the layer wiring and the pad electrode are interposed
In a semiconductor device in which the pad electrode is in contact without being embedded therein, the pad electrode has a different size in contact with the arbitrary wiring.
Is connected to the arbitrary wiring by a plurality of connection holes
A semiconductor device characterized in that 4. The pad electrode and the pad electrode in the pad electrode.
Characterized by arranging polishing stoppers made of different materials
The semiconductor device according to claim 3. 5. A connecting means and a pad for electrically connecting with an external device.
Has a substantially flat surface immediately below the connection with the electrode
There is a power supply for the switching element arranged for each pixel electrode.
Is an arbitrary wiring among the wirings of multiple layers for transmitting a signal and the wiring
Active mat that contacts the dead electrode without incorporating inclusions
In the lix substrate, the pad electrode has a different size in contact with the arbitrary wiring.
Is connected to the arbitrary wiring by a plurality of connection holes
An active matrix substrate characterized in that 6. The pad electrode and the pad electrode in the pad electrode.
Characterized by arranging polishing stoppers made of different materials
The active matrix substrate according to claim 5.