JP2000194008A - Image display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a seal region for realizing uniform liquid crystal cell gap and a manufacturing method thereof. SOLUTION: A semiconductor element having the same shape as a display region 30 is formed in the seal region 32. Thereby average height of substrate surfaces in the seal region 32 before metal CMP and in the display region 30 are equalized. Consequently both heights after metal CMP can be equalized and further global flatness of whole surfaces of the substrates can be obtained. Precise control of gap at the time of forming a liquid crystal panel can be executed due to improvement of global flatness of the substrates. Since it is unnecessary for the semiconductor element formed in the seal region 32 to perform electrical action such as circuit action, contact holes connecting a source region 4, a drain region 5, low concn. n-layer 7, low concn. p-layer 8 and an electrode (AL1) 12 with a semiconductor substrate can be omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device and a method for manufacturing the same, and more particularly, to a method in which a surface of a pixel electrode arranged in a matrix on a counter substrate side and a surface of a mounting region on a counter substrate side substantially correspond to each other. TECHNICAL FIELD The present invention relates to an image display device which is coplanar and flat.

[0002]

2. Description of the Related Art A conventional display device is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-179377, as shown in FIGS. FIG. 10 is a sectional view of FIG. In the figure, 1
01 is a display pixel area, 102 is a dummy pixel, 103 is a signal / scan drive circuit, and 104 is a semiconductor substrate. The active matrix substrate of the reflection type liquid crystal display device used in the conventional enlarged projection display device, as shown in the above-described conventional example, has a sag around a display area caused by chemical mechanical polishing (CMP: chemical mechanical polishing). To prevent this, the display area is kept flat by arranging a dummy pixel area around the display area, and the light reflectance is made uniform in the entire display area.

A liquid crystal cell of a liquid crystal display device used in such a conventional enlarged projection display device has an active matrix substrate, a counter substrate and both substrates adhered to each other, and the liquid crystal is sandwiched between cells formed by a seal for enclosing the liquid crystal. It is configured to be enclosed.

The cell gap of several μm between which the liquid crystal is sandwiched is controlled by disposing a spacer having the same diameter as the desired cell gap between the two substrates. The place where this spacer is arranged is desirably a place other than the image display area in the liquid crystal panel used in the enlarged projection display device. This is because, when a spacer for controlling the gap of the liquid crystal cell is arranged in the display area, the spacer itself or the alignment defect of the liquid crystal caused by the spacer becomes apparent on the display image by the enlarged projection, thereby deteriorating the image quality. .

Therefore, in an enlarged projection type liquid crystal display device, generally, no spacer is provided in a display area, a liquid crystal cell is formed by a seal in which spacers are mixed, and a gap is controlled by the spacer provided in the seal region. It has a configuration.

[0006]

However, in the prior art, the flatness in the display area is maintained by a dummy pixel area provided around the display area, but the display area is not provided in other peripheral circuits, seal areas, and the like. Will be different.

This is attributable to the fundamental polishing characteristics of chemical mechanical polishing (CMP: chemical mechanical polishing). In other words, the polishing cloth used for CMP is an elastic body, and the polishing cloth, which is an elastic body, deforms and follows irregularities such as large undulations from several hundred μm to several mm. It will remain almost as originally. Especially in the case of metal CMP, a soft abrasive cloth,
That is, the use of a polishing cloth that is easily deformed causes the above-described phenomenon to be prominent.

[0008] The irregularities such as large undulations ranging from several hundreds of μm to several mm on the substrate surface have different average surface heights due to different pattern densities in the display area, peripheral circuit area, and seal area. Due to that.
This average height difference will remain as global irregularities even after polishing by CMP.

As a result, the heights of the seal area and the display area are different, and it is difficult to stably realize the set cell gap.

Also, if there is a difference in the density of the pattern depending on the location even in the sealing region for controlling the gap of the liquid crystal cell, unevenness occurs, and it is difficult to realize a uniform cell gap.

The non-uniformity of the liquid crystal cell gap affects the VT characteristics of the liquid crystal. As a result, the brightness of the displayed image becomes non-uniform, and the display color becomes non-uniform. This causes image defects such as color unevenness and causes deterioration of a displayed image.

Accordingly, an object of the present invention is to provide a structure of a sealing region for realizing a uniform liquid crystal cell gap and a method of manufacturing the same.

[0013]

In order to achieve the above object, the present invention provides a pixel electrode arranged in a matrix,
An active matrix substrate including a switching element disposed on each of the pixel electrodes, and a signal scanning drive circuit for driving the switching element; a counter electrode substrate bonded to the active matrix substrate so as to face the active matrix substrate; And a liquid crystal sandwiched between the opposing electrode substrates, wherein the surface of the pixel electrodes arranged in a matrix on the opposing substrate side, and a mounting area in which the switching element is mounted Chemical mechanical polishing (CMP) is performed so that the surface on the counter substrate side is substantially coplanar.
chemical polishing).

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a sectional structure of a liquid crystal panel according to the present invention. In the figure, 1 is a p-type semiconductor substrate, 2 is a p-type well, 3 is an n-type well, 4 is a source region of a transistor, 5 is a drain region, and 6 is a gate electrode. As shown in FIG. 1, since a high voltage of 20 to 35 V is applied to the transistor in the display region 30, the source and drain regions are not formed in a self-aligned manner with respect to the gate 6. N layer 7 and a low concentration p layer are provided. By the way, the offset amount is 0.
5-2.0 μm is preferred. Here, the offset amount of the source and the drain may be changed according to a desired breakdown voltage,
Optimization of the gate length is effective. This is the peripheral circuit 31
Is a logic circuit, and this part is generally 1.
Since the driving of 5 to 5 V is sufficient, a high pixel display can be realized by optimizing the driving force, speed, and the like of the transistor size according to each.

In FIG. 1, reference numeral 9 denotes a field oxide film;
0 is a gate oxide film, 11 is an interlayer insulating film such as BPSG, 1
2 is an electrode (AL1), 13 is plasma SiO_TwoEtc. between layers
Insulating film, 14 is flat such as SOG or ozone TEOS
Film 15 is plasma SiO _TwoAnd the like.
Here, in order to improve the flatness of the Si chip, interlayer insulation is required.
A method of performing CMP treatment on the edge film 15 is also effective.

The light-shielding layer 16 covers the display area 30, the peripheral circuit area 31, and the seal area 32, and includes Ti, TiN, W, and Mo.
And the like. In the pixel region 30, the light-shielding layer 16 has the electrodes (A
L1), but the peripheral circuit area 3
In No. 1, the light-shielding layer 16 is excluded in a portion where the wiring capacitance becomes large, such as a video line and a clock line. In the peripheral circuit region 31 except for the light-shielding layer 16, dummy electrodes 19 are provided to prevent malfunction of the circuit due to the incidence of illumination light.
There is a device for placing

Reference numeral 17 denotes an interlayer insulating film which is sandwiched between the pixel electrode 18 and the electrode of the light-shielding layer 16 to form a storage capacitor for the pixel electrode, and is made of a dielectric material having a large dielectric constant, such as Si ₃ N ₄ or Ta ₂ O _5. Is suitable.

The pixel electrode 18 is preferably made of a metal material such as AL, Ag, Cr, and Pt which has a high reflectance with respect to visible light. Although not shown here, there is a method of improving the reflectance by forming a dielectric multilayer film such as Ti oxide on the surface of the pixel electrode 18.

Here, a method of forming the pixel electrode 18 and the dummy electrode will be described. After patterning the light-shielding layer 16, an interlayer insulating film 17 and an insulating film 20 are successively stacked and formed. Here, Si ₃ is formed on the interlayer insulating film 17 by plasma CVD.
2500 Å of N ₄ and 10,000 Å of SiO _{2 formed} by plasma CVD on the insulating film 20 are not limited to these materials and film thicknesses. The insulating film 20 is etched using the patterned photoresist as a mask. As an etching method, for example, dry etching using CF ₄ and CHF ₃ gases can be applied. In this etching, it is better to increase the etching selectivity between the insulating film 20 and the interlayer insulating film 17 so that the interlayer insulating film 17 functions as an etching stopper. Therefore, it is preferable to increase the deposition gas CHF ₃ and set the etching pressure to a relatively high pressure. In this case, CHF ₃ : CF ₄ = 80: 2
The etching conditions were such that the etching rate of the insulating film 20 was 1/3 of the etching rate of the interlayer insulating film 17 by setting the pressure to 0 and the pressure to 1.7 Torr. The insulating film 20 is patterned by the above method to form a groove in which the pixel electrode and the dummy electrode are formed.

Next, a through-hole for forming a connection between the pixel electrode and the electrode (AL1) is formed. At this time, it is not necessary to form through holes for the dummy electrodes in the peripheral circuit region 31 and the seal region 32 that do not need to be electrically connected to the electrode (AL1).

Subsequently, a pixel electrode material is formed on the entire surface of the substrate. Here, for the purpose of simultaneously filling the through-holes simultaneously with the formation of the pixel electrode material, TIN is formed by a sputtering method of 500 Å, Ti is formed by a sputtering method of 300 Å, and pure AL is formed.
Was formed into a film having a thickness of 10,000 Å by high-temperature reflow sputtering at 485 ° C. TIN is a barrier layer for protecting the interlayer insulating film 17 which is a capacitance film, and Ti is pure AL.
This is for improving the reflow property. This step is not limited to the above method, and the through hole is formed by tungsten CV.
A method of embedding with D and subsequently forming an AL film by ordinary sputtering is also effective.

Finally, the electrode material formed on the insulating film 20 is scraped off by metal CMP, and the adjacent electrodes are insulated and separated, and at the same time, the surfaces of the pixel electrodes 18 and the dummy electrodes 19 are formed flat. In this metal CMP, SUPREME, RN made by Rodale Nitta is used for the polishing cloth.
-H, Fujimi PLANERLITE 510 slurry
2. EPO114 manufactured by EBARA CORPORATION as a CMP apparatus, load 300 gf / cm ² as polishing conditions, table rotation speed 30 r
pm and a wafer carrier rotation speed of 31 rpm. Note that the CMP conditions are not limited to the above conditions. Cleaning after CMP is megasonic cleaning with pure water,
Pure water scrub cleaning using a PVA brush was also used.

As shown in FIG. 1, the liquid crystal cell is constituted so that a liquid crystal 22 is sandwiched between a semiconductor substrate 1 and a transparent substrate 24, 21 is an alignment film, 23 is a transparent electrode such as ITO,
Reference numeral 26 denotes a sealing material for enclosing liquid crystal.

The sealing material 26 is made of a curable resin such as an epoxy resin, a phenol resin, a urethane resin, and the like. The curing method may be selected depending on the purpose, action, and effect, such as thermosetting, ultraviolet curing, and curing using both heat and ultraviolet. The desired one is used. In addition, sticking printing, drawing using a dispenser, or the like is applied to these coating methods. Further, a spacer for controlling the gap between the semiconductor substrate 1 and the transparent substrate 24 is mixed in the sealing material 26, and the gap between the liquid crystal cells is controlled at the same time as the two substrates are bonded.

The liquid crystal 22 has a TN mode, a VA mode,
A liquid crystal such as PNLC or PDLC can be used without the alignment film 21.

Reference numeral 25 denotes a stress adjusting film for controlling the warpage of the semiconductor substrate 1, and here, Si _{3 formed} by low pressure CVD.
1500 Å of N ₄ was applied. The stress adjusting film 25 is not limited to the above-mentioned material and film thickness, and is capable of suppressing warpage of the semiconductor substrate 1 resulting from lamination of films having various stresses formed on the substrate surface in a semiconductor manufacturing process. This is a film for complementation, in which a film of a desired thickness or a tensile stress or a compressive stress is formed for each semiconductor process. The above-mentioned low pressure CVD is used as the film of the tensile stress.
Si ₃ N ₄ and thermally oxidized SiO ₂ are examples of a film having a compressive stress. The reason why the warpage of the semiconductor substrate 1 must be complemented will be described below. In a liquid crystal panel used in an enlarged projection display device, the gap must be controlled in a seal region. This is because when a spacer for controlling the gap is arranged in the display area, the spacer deteriorates the image quality of the display image enlarged and projected, and the disorder of the alignment of the liquid crystal caused by the spacer is also manifested by the enlarged projection and the image quality is significantly deteriorated. To do that.

In the case where the gap of the liquid crystal panel is controlled only by the seal area, it is very difficult to uniformly control the gap in the display area if either the semiconductor substrate 1 or the transparent substrate 24 is concave or convex. Becomes
Even when the substrates are forcibly corrected for warpage and bonded together, and the sealing material is cured at the same time, the two substrates and the sealing material constituting the liquid crystal cell are elastic, so they are each deformed by the residual internal stress. This is because

The allowable amount of the substrate warpage is, for example, when each of the diagonal 1.8 inch substrates is controlled to have a gap of 3 ± 0.3 μm, it depends on the material and the substrate bonding apparatus. Warpage must be suppressed to ± 0.3 μm or less.

FIG. 2 is a block diagram of a panel peripheral circuit. In FIG. 2, reference numeral 337 denotes a display area of the liquid crystal element;
2 is a level shifter circuit, 333 is a video signal sampling switch, 334 is a horizontal shift register, 335 is a video signal input terminal, and 336 is a vertical shift register.

With the configuration described above, a logic circuit such as a shift register for both H and V is connected to the video signal input terminal 3
Since an amplitude of about 35 to 25 V and 30 V is supplied,
It can be driven at an extremely low value of about 1.5 to 5 V, and high speed and low voltage consumption can be achieved. Here, the horizontal and vertical SR are
The scanning direction can be bi-directionally controlled by a selection switch, so it is possible to respond to changes in the arrangement of optical systems, etc. without changing the panel, and the same panel can be used for different series of products, reducing cost. There are merits that can be achieved. In FIG. 18, the video signal sampling switch is
Although a one-polarity one-transistor configuration has been described, it is needless to say that the input video lines can all be written to the signal lines by using a CMOS transmission gate configuration.

Further, when the CMOS transmission gate structure is used, there is a problem that a video signal is fluctuated due to a difference between an NMOS gate and a PMOS gate area and an overlap capacitance between the gate and the saw drain. This can be prevented by connecting the source and the drain of the MOSFET having a gate amount of about 1/2 of the gate amount of the MOSFET of the sampling switch of each polarity to the signal line, respectively, and applying a reverse phase pulse, thereby preventing the swing. A very good video signal was written to the signal line. As a result, higher-quality display is possible.

FIG. 3 is a plan view of the image display unit for explaining the relationship between the seal structure and the panel structure. In FIG. 3, reference numeral 351 denotes a sealing portion, 352 denotes an electrode pad, and 353 denotes a sealing portion.
Is a clock buffer circuit. An amplifier unit (not shown) is used as an output amplifier at the time of panel electrical inspection. In addition, there is a conductive paste portion (not shown) for taking the potential of the opposing substrate, and 356 is a display portion of a liquid crystal element,
Denotes a peripheral circuit section such as a horizontal / vertical shift register (SR). A seal portion 351 indicates a contact area of a bonding material or an adhesive for bonding a pixel electrode 312 provided on the semiconductor substrate 301 around the display portion 356 and a glass substrate provided with the common electrode 315. After bonding by the unit 351, the display unit 356 and the shift register unit 357
The liquid crystal is sealed in.

As shown in FIG. 3, in the present embodiment, both the inside and outside of the seal are total chip sips.
A circuit is provided to reduce ze. In this embodiment, the pad drawers are concentrated on one side of the panel. However, both sides on the long side can be taken out from multiple sides instead of one side. Sometimes effective.

Further, since the panel of the present invention uses a semiconductor substrate such as a Si substrate, strong light is irradiated as in a projector, and when light is applied to the side wall of the substrate, the substrate potential fluctuates. Panel malfunction may occur. Therefore, the side wall of the panel and the peripheral circuit portion of the display area on the upper surface of the panel are a substrate holder capable of shielding light, and the back surface of the Si substrate has a high thermal conductivity through an adhesive having a high thermal conductivity. It has a holder structure in which metals such as Cu are connected.

FIG. 4 is an optical path diagram of an optical system incorporating the reflection type liquid crystal panel of the present invention. In FIG.
1 is a light source such as a halogen lamp, 372 is a condenser lens for narrowing down a light source image, 373 and 375 are planar convex Fresnel lenses, 374 is a color separation optical element for separating into R, G, and B, and a dichroic mirror. A diffraction grating or the like is effective.

A mirror 376 guides each light separated into R, G, and B light to the R, G, and B panels, and a mirror 377 illuminates the condensed beam to the reflection type liquid crystal panel with parallel light. The field lens 378 has an aperture at the position of the reflective liquid crystal element 379 described above. 380 is a projection lens that expands by combining a plurality of lenses, and 381 is a screen, which is usually composed of two plates: a Fresnel lens that converts projection light into parallel light, and a lenticular lens that displays a wide viewing angle vertically and horizontally. As a result, a clear, high-contrast, bright image can be obtained. Although only one color panel is described in the configuration of FIG. 4, the space between the color separation optical element 374 and the squeezing portion 379 is separated into three colors, and a three-panel panel is arranged. Further, it is needless to say that not only three plates but also a single plate configuration is possible by providing a microlens array on the surface of the reflective liquid crystal device panel and irradiating different incident lights to different pixel regions. A voltage is applied to the liquid crystal layer of the liquid crystal element, and the light that has been specularly reflected at each pixel is transmitted through the squeezed portion 379 and projected on the screen.

FIG. 5 is a block diagram of a peripheral electric circuit other than the liquid crystal panel. In FIG. 5, 385 is a power supply,
It is mainly divided into a lamp power supply and a system power supply for driving panels and signal processing circuits. Reference numeral 386 denotes a plug, and 387 denotes a lamp temperature detector. When there is an abnormality in the lamp temperature, the control board 388 controls the lamp to stop. This is controlled not only by the lamp but also by the 389 filter safety switch. For example, if a high-temperature lamp house box is to be opened, safety measures are taken to prevent the box from opening. Reference numeral 390 denotes a speaker, and 391 denotes an audio board. A processor for 3D sound, surround sound, or the like can be incorporated as required.
Reference numeral 392 denotes an expansion board 1, which is an S terminal for video signals, an input terminal for an external device 396 such as a composite video and audio signal for video signals, and a selection switch 3 for selecting which signal to select.
95, a tuner 394, and a signal is sent to the expansion board 2 via the decoder 393. On the other hand, expansion board 2
Mainly consists of videos from different affiliates and computer Ds
The digital signal is converted by an A / D converter 451 through a switch 450 that has a ub15 pin terminal and switches the video signal from the decoder 398.

A main board 453 mainly comprises a memory such as a video RAM and a CPU. The NTSC signal that has been A / D converted by the A / D converter 451 is temporarily stored in a memory, and is created by interpolating a signal of a vacant element shortage that does not match the number of liquid crystal elements in order to assign it to a high number of pixels. And performs signal processing such as gamma conversion edge gradation and brightness adjustment bias adjustment suitable for the liquid crystal display element.
Not only NTSC signals but also computer signals such as V
If a GA signal comes, in the case of a high resolution XGA panel,
The resolution conversion process is also performed. Not only one image data,
The main board 453 also performs processing such as combining a computer signal with an NTSC signal of a plurality of image data. The output of the main board 453 is subjected to serial / parallel conversion, and is applied to the head board 454 in a form that is less affected by noise. The head board 454 performs D / A conversion after parallel / serial conversion again, divides according to the number of video lines on the panel, and
A signal is written to the liquid crystal panels 455, 456, and 457 of B, G, and R colors. Reference numeral 452 denotes a remote control operation panel, and a computer screen can be easily operated with the same feeling as a TV. Further, each of the liquid crystal panels 455, 456, and 457 has the same liquid crystal device configuration provided with a color filter of each color, and the horizontal and vertical scanning circuits described in the first to fifth embodiments are applied. As described above, since each liquid crystal device processes an image that does not always have high resolution into high-quality image by processing, the display result of the present invention can display an extremely clear image.

The feature of this embodiment is that a semiconductor element having the same shape as the display area 30 is formed in the seal area 32. As a result, the average height of the substrate surface of the seal region 32 and the display region 30 before the metal CMP are equalized. As a result, both heights after the metal CMP can be equalized. It is possible to obtain excellent flatness. By improving the global flatness of the substrate, precise control of the gap when forming a liquid crystal panel becomes possible.

Since the semiconductor element formed in the seal region 32 does not need to operate electrically such as circuit operation, the source region 4, the drain region 5, the low-concentration n-layer 7, the low-concentration p-layer 8, and the electrode (AL1) It is also possible to omit the contact hole connecting the semiconductor substrate 12 to the semiconductor substrate.

As described above, as a result of obtaining a uniform gap in the liquid crystal panel, it is possible to realize a magnified projection type liquid crystal display device having clear image quality without unevenness in brightness and color of a displayed image. or,
Since the yield of the step of controlling the gap of the liquid crystal panel can be improved, the cost of the liquid crystal panel can be reduced.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention. Hereinafter, the structure of the seal region 32 of the present embodiment will be described. An n-type well 3 is formed in the p-type semiconductor substrate 1 in the seal region 32. This is because even when the interlayer film of the sealing region 32 is mechanically broken by the spacer included in the sealing material 26 when the interlayer film is bonded to the opposing substrate 24, a failure that an electric leak path occurs in the interlayer film occurs. ,
The purpose is to isolate the semiconductor substrate 1 from the leak path by the n-type well. Here, an example of a p-type semiconductor substrate is shown, but when an n-type semiconductor substrate is used, a p-type well may be formed.

Next, a field oxide film 9 is formed on the surface by thermal oxidation. This is to increase the thickness of the insulating layer and increase the mechanical resistance during bonding.

The electrode 12 (AL1) is patterned into any desired shape. This will be described in detail later.

The light shielding layer 16 is formed of the light shielding layer 16 of the display area 30.
And is electrically isolated and electrically floating. This is to prevent the light-shielding layer 16 from serving as a power supply for the leak even if a leak path occurs in the interlayer film described above.

The feature of this embodiment is that the average height per unit area of the seal region 32 before the CMP is set to the display region 3.
This is a point adjusted to an average height per unit area of 0.

Here, the unit area is an arbitrary area, and is preferably 0.5 to several mm ^{2 in} practice, but is not limited to this. On the other hand, the height means here the pixel electrode 18 and the dummy electrode 19, which are the surface of the active matrix substrate before the CMP from the bottom surface of the field oxide film 9.
The distance to the surface of the electrode material to be formed was defined as The height is not limited as long as it is a distance from an arbitrary reference plane to the substrate surface.

Here, how to determine the average height of the substrate surface will be specifically described with reference to the display area 30 in FIG.

The unit area for obtaining the average height is 1 mm ²
And When the thickness of the field oxide film 9 is 5000 angstroms and its ratio to the unit area is 80%, the average height T (Field) of the field oxide film 9 is
d) is T (Field) = 5000 Å ×
0.8 = 4000 angstroms. Similarly, when the thickness of the gate electrode 6 is 4400 angstroms and the area ratio is 10%, the average height T of the gate electrode 6 is
(Poly) is 4400 angstroms x 0.1 =
It will be 440 angstroms.

When the thickness of the interlayer insulating film 11 is 7000 angstroms and the area ratio is 98%, the average height T (ILD1) of the interlayer insulating film is 7000 angstroms × 0.98 = 6860 angstroms. .

The thickness of the electrode 12 (AL1) is 6000
When the area ratio is 70% in Angstroms, the average height T (AL1) of the electrode 12 (AL1) is 6000
Angstrom × 0.7 = 4200 angstrom.

The interlayer insulating films 13 and 15 and the planarizing film 1
4 has a total thickness of 11,000 angstroms and an area ratio of 99%, the average height T (ILD
2) is 11000 angstroms × 0.99 = 10
890 angstroms.

When the thickness of the light shielding layer 16 is 3000 angstroms and the area ratio is 95%,
Average height T (TI) is 3000 Å ×
0.95 = 2850 angstroms.

When the thickness of the insulating film 20 is 10000 angstroms and the area ratio is 10%,
The average height T (ILD3) of 0 is 10,000 Å × 0.1 = 1000 Å.

When the thickness of the pixel electrode 18 and the dummy electrode 19 is 12,000 Å, the electrode height T (AL2) is 1 because the film is formed on the entire surface of the substrate.
2000 angstrom × 1.0 = 12000 angstrom.

Assuming that the value obtained by adding the average heights of all the layers is the average substrate surface height before CMP T (AVE), T (AVE) is (T (Field) + T (Pol)
y) + T (ILD1) + T (AL1) + T (ILD2)
+ T (TI) + T (ILD3) + T (AL2)) = 42
240 Angstroms.

As a method for realizing the features of the present embodiment, the electrode (AL1) 12 is formed in a desired arbitrary pattern. By setting the pattern width, the space width, and the pattern density of the electrode 12 (AL1) to desired values, it is possible to make the average height of both regions before CMP uniform.

Specifically, the electrode 12 in the sealing region 32
The pattern formation guideline of (AL1) will be described. In this seal region 32, the gate electrode 6 is not arranged,
Since the layers other than the electrode (AL1) 12 and the insulating film 20 are not patterned, the sum T (1) of their average heights
Is (T (Field) + T (ILD1) + T (ILD
2) + T (TI) + T (AL2)) = (5000 angstroms + 7000 angstroms + 11,000 angstroms + 3000 angstroms + 1200)
0 angstrom) = 38000 angstrom.

Assuming that the pattern of the insulating film 20 is the same as that of the display region 30, T (ILD3) becomes 1000 Å.

Accordingly, assuming that the average height excluding the electrode 12 (AL1) is T (2), T (2) is (T (1) + T (2)).
(ILD3)) = 39000 angstroms.

The electrode 12 (AL
The target average height T (AL1) ′ of 1) is T (AL1).
1) '= (T (AVE) -T (2)) = (42240 angstroms-39000 angstroms) = 32
It will be 40 angstroms.

The electrode 12 (AL
If the area ratio of 1) is R (AL1), then R (AL1) = 3240 Å / 6000 Å = 54%. Therefore, by patterning the sealing area 32 so that the area ratio of AL1 per unit area is 54%, the heights of both the areas before the CMP can be made uniform. As a result, the heights of the two areas after the CMP can be adjusted. It becomes possible to make the same. This electrode 12 (AL1)
It is more effective to arrange the patterns uniformly without uneven distribution in the assumed unit area in terms of planarization of CMP.

FIG. 7 shows a measurement result of the surface height distribution after the CMP of the active matrix substrate to which the present embodiment is applied.
(A) and FIG. 7 (b). FIG. 7A is a plan view of the active matrix substrate, and FIG. 7B is a plan view of FIG.
Is the result of measuring the substrate height at the AA 'part of FIG.

As a comparison, the electrode 12 in the seal region 32
FIG. 8 shows a measurement result of the substrate surface height distribution after the CMP of the conventional substrate in which (AL1) is not patterned and the other layers are the same as the above example.

From these results, it is found that the surface roughness of the substrate after CMP in the substrate to which the present embodiment is applied is 1000 Å or less, and the surface
It can be seen that higher flatness is obtained as compared with 00 angstrom.

In the present embodiment, an example is shown in which the height of both regions is made uniform by patterning the electrode 12 (AL1) into a desired shape. However, the present invention is not limited to this. A similar effect can be realized by processing a layer capable of forming a desired step shape by patterning such as 16. Furthermore, the combined use of the processing of a plurality of layers makes it possible to more precisely align the heights of both regions.

When the above method is applied to the peripheral circuit region 31, flattening is realized over the entire surface of the substrate, which is effective for precise gap control.

The above-mentioned average height before the CMP does not have to be adjusted without any difference. If the final height distribution falls within the allowable range of the product performance, the average height is within the allowable range. It is also possible to fluctuate.

Although two embodiments of the present invention have been described above, the present invention is not limited to these embodiments.
Needless to say, the effect is increased by combining the techniques of the mutual forms.

In particular, although the structure of the liquid crystal panel is described using a semiconductor substrate, it is not necessarily limited to a semiconductor substrate, and the structure described below is formed on a normal transparent substrate. You may.

The liquid crystal panels are all MOSFET or TFT types, but may be two-terminal types such as diode types.

The liquid crystal panel is effective as a display device for a home television, a projector, a head mounted display, a three-dimensional video game machine, a laptop computer, an electronic organizer, a video conference system, a car navigation system, an airplane panel, and the like. It is.

[0074]

According to the present invention described above, high flatness of the surface of the active matrix substrate can be realized without being restricted by the pattern, the yield of the bonding step can be improved, and the product cost can be reduced. In addition, since the gap between the liquid crystal cells is formed uniformly, a clear image display without color and luminance unevenness is realized. That is, the active matrix substrate after the substrate surface is flattened by the CMP realizes global flatness over the entire substrate surface, and as a result, a liquid crystal panel with good uniformity of the liquid crystal cell gap and good reproducibility is realized. it can. As a result, the image display device such as the magnified projection display according to the present invention realizes a clear image with uniform brightness and color on the screen.

[Brief description of the drawings]

FIG. 1 is a sectional view of a liquid crystal panel according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a peripheral circuit of the liquid crystal panel according to the first embodiment of the present invention.

FIG. 3 is a plan view of the liquid crystal panel according to the first embodiment of the present invention.

FIG. 4 is an optical system of a display device incorporating the liquid crystal panel according to the first embodiment of the present invention.

FIG. 5 is an electric circuit diagram of a display device incorporating the liquid crystal panel according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a liquid crystal panel according to a second embodiment of the present invention.

FIG. 7A is a plan view of a liquid crystal panel. (B) is a graph showing the result of measuring the substrate height at the AA 'part of (a) of the liquid crystal panel according to the second embodiment of the present invention.

8 is a graph showing the result of measuring the substrate height of the conventional liquid crystal panel at the AA 'portion in FIG. 7A.

FIG. 9 is a plan view of a conventional liquid crystal panel.

FIG. 10 is a cross-sectional view of a conventional liquid crystal panel.

[Explanation of symbols]

 Reference Signs List 1 p-type semiconductor substrate 2 p-type well 3 n-type well 4 source region 5 drain region 6 gate electrode 7 low-concentration n-layer 8 low-concentration p-layer 9 field oxide film 10 gate oxide film 11 interlayer insulating film 12 electrode (AL1) 13 Interlayer insulating film 14 Flattening film 15 Interlayer insulating film 16 Light shielding film 17 Interlayer insulating film 18 Pixel electrode 19 Dummy electrode 20 Insulating film 21 Alignment film 22 Liquid crystal 23 Transparent electrode 24 Transparent substrate 25 Stress adjusting film 26 Sealing material 30 Display area 31 Peripheral Circuit area 32 Seal area 332 Level shifter circuit 333 Video signal sampling switch 334 Horizontal shift register 335 Video signal input terminal 336 Vertical shift register 337 Display area 351 Seal section 352 Pad 353 Buffer 356 Display section 357 Peripheral circuit section 371 Light source 372 Optical lens 373 Fresnel lens 374 Color separation optical element 375 Fresnel lens 376 Color separation mirror 377 Field lens 378 Liquid crystal panel 379 Squeezing 380 Projection lens 381 Screen 385 Power supply 386 Plug 387 Lamp temperature detector 388 Control board 389 Filter safety switch 390 Speaker 391 Voice Board 392 Extension board 2 393 Decoder 394 Tuner 395 Selection switch 396 External device 450 Switch 451 A / D converter 452 Operation panel 453 Main board 454 Head board 455 B color panel 456 G color panel 457 R color panel 101 Display pixel area 102 Dummy pixel 103 signal / scan drive circuit 104 semiconductor substrate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 HA07 JA01 JA24 JB09 MA05 MA07 MA08 MA31 NA19 NA24 NA27 NA29 PA01 PA07 RA05 5C094 AA03 AA42 AA55 BA03 BA16 BA43 CA19 DA12 DA13 EA04 EA05 EC02 FA01 FA02 GB01 GB10

Claims (5)

[Claims] 1. A pixel electrode arranged in a matrix,
An active matrix substrate including a switching element disposed on each of the pixel electrodes, and a signal scanning drive circuit for driving the switching element; a counter electrode substrate bonded to the active matrix substrate so as to face the active matrix substrate; And a liquid crystal sandwiched between the opposing electrode substrates, wherein the surface of the pixel electrodes arranged in a matrix on the opposing substrate side and a mounting area on which the switching element is mounted An image display device, wherein the surface on the counter substrate side is substantially coplanar. 2. The image display device according to claim 1, wherein a structure having substantially the same shape as the switching element is arranged in at least a part of the mounting area. 3. The image display device according to claim 1, wherein a structure processed into an arbitrary shape is arranged in at least a part of the mounting area. 4. The image display device according to claim 1, wherein said switching element is made of a semiconductor. 5. The method according to claim 1, wherein the step of forming the pixel electrode and the mounting region includes a polishing step by chemical mechanical polishing (CMP: chemical mechanical polishing). 3. A method for manufacturing an image display device according to claim 1.