KR880003419A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR880003419A
KR880003419A KR1019870008811A KR870008811A KR880003419A KR 880003419 A KR880003419 A KR 880003419A KR 1019870008811 A KR1019870008811 A KR 1019870008811A KR 870008811 A KR870008811 A KR 870008811A KR 880003419 A KR880003419 A KR 880003419A
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KR
South Korea
Prior art keywords
chip
layers
regions
semiconductor device
insulating layer
Prior art date
Application number
KR1019870008811A
Other languages
English (en)
Other versions
KR910004617B1 (ko
Inventor
다게히데 시라또
데루오 다주노끼
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR880003419A publication Critical patent/KR880003419A/ko
Application granted granted Critical
Publication of KR910004617B1 publication Critical patent/KR910004617B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명에 따른 첫번째 실시예의 반도체 장치의 요부를 보인 평면도.
제6(A)도는 제5도의 라인 VIA-VIA를 따라 취한 단면도.
제6(B)도는 제5도의 라인 VIB-VIB를 따라 취한 단면도.
제7도는 크래크들이 있는 상태에서, 제5도의 라인 VIA-VIA를 따라 취한 횡단면도.

Claims (5)

  1. 반도체 장치에 있어서, 반도체 칩이 반도체 칩 가장자리 근처에서의 주변 영역들에서 배열되는 메인 공급 선들을 가지고, 상기 메인 전원선들이 절연층을 사이에 내재하고 있는 다층 레벨 층들로 형성되고, 그 각각의 상기 메인전원 선들은 상기 반도체 칩의 코너들에 인접한 칩 코너 영역들에서 상기 절연층을 거쳐서 동일 전위를 갖는 충돌이 맞대어 배열되도록 형성되는, 상기 반도체 칩은 밀패시키는 플라스틱으로 만들어지는 패키지등을 포함하는 반도체 장치.
  2. 청구범위 제1항에 있어서, 상기 코너 영역들에서 동일 전위를 갖는 상기 층들이 동일 전위를 갖는 상기 층들 사이에서 샌드위치 되는 상기 절연층에서 형성된 관통호올 안으로 채워지는 금속재료의 수단에 의하여 전기적으로 연결되는 반도체 장치.
  3. 청구범위 제1항에 있어서, 상기 칩 코너 영역들에서 형성된 동일 전위를 갖는 상기 층들이 상기 칩 코너 영역들 이외의 영역들에서 칩 코너 영역들의 다른 부분들 보다 좁은 반도체 장치.
  4. 청구범위 제1항에 있어서, 상기 칩 코너 이외의 영역들에서, 상기 메인전원 공급 선들이 상기 절연층을 거쳐서 다른 전위를 갖는 층들이 서로 맞대어 배열 형성되는 반도체 장치.
  5. 청구 범위 제1항에 있어서, 상기 메인전원공급 선들이 상기 반도체 칩의 가장자리 근처 주변 영역들에서 집중적으로 형성되는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870008811A 1986-08-12 1987-08-11 반도체 장치 KR910004617B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP189095 1984-09-10
JP61-189095 1986-08-12
JP61189095A JPS6344742A (ja) 1986-08-12 1986-08-12 半導体装置

Publications (2)

Publication Number Publication Date
KR880003419A true KR880003419A (ko) 1988-05-17
KR910004617B1 KR910004617B1 (ko) 1991-07-08

Family

ID=16235256

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870008811A KR910004617B1 (ko) 1986-08-12 1987-08-11 반도체 장치

Country Status (5)

Country Link
US (1) US4914503A (ko)
EP (1) EP0259631B1 (ko)
JP (1) JPS6344742A (ko)
KR (1) KR910004617B1 (ko)
DE (1) DE3785899T2 (ko)

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JPH0789568B2 (ja) * 1986-06-19 1995-09-27 日本電気株式会社 集積回路装置
JP2752098B2 (ja) * 1988-09-20 1998-05-18 三洋電機株式会社 半導体集積回路
KR920005863B1 (ko) * 1988-08-12 1992-07-23 산요덴끼 가부시끼가이샤 반도체 집적회로
JPH02163960A (ja) * 1988-12-16 1990-06-25 Toshiba Corp 半導体装置
US5185650A (en) * 1989-02-28 1993-02-09 Kabushiki Kaisha Toshiba High-speed signal transmission line path structure for semiconductor integrated circuit devices
JP2724193B2 (ja) * 1989-02-28 1998-03-09 株式会社東芝 半導体装置
EP0482194A4 (en) * 1989-06-26 1992-05-06 Oki Electric Industry Co., Ltd. Wiring structure of semiconductor chip
JPH0364735A (ja) * 1989-08-03 1991-03-20 Sharp Corp アクティブマトリクス表示装置
JPH0831455B2 (ja) * 1990-01-23 1996-03-27 三洋電機株式会社 半導体集積回路
US5378925A (en) * 1990-07-23 1995-01-03 Seiko Epson Corporation Routing method and arrangement for power lines and signal lines in a microelectronic device
DE4115909C1 (ko) * 1991-05-15 1992-11-12 Siemens Ag, 8000 Muenchen, De
US5391920A (en) * 1991-07-09 1995-02-21 Yamaha Corporation Semiconductor device having peripheral metal wiring
JP3185271B2 (ja) * 1991-09-13 2001-07-09 日本電気株式会社 半導体集積回路
JP3432963B2 (ja) * 1995-06-15 2003-08-04 沖電気工業株式会社 半導体集積回路
US5789783A (en) * 1996-04-02 1998-08-04 Lsi Logic Corporation Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection
JPH10198292A (ja) * 1996-12-30 1998-07-31 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6191475B1 (en) * 1997-11-26 2001-02-20 Intel Corporation Substrate for reducing electromagnetic interference and enclosure
JP4330676B2 (ja) * 1998-08-17 2009-09-16 株式会社東芝 半導体集積回路
JP2001053283A (ja) 1999-08-12 2001-02-23 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
US7023021B2 (en) 2000-02-22 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4118484B2 (ja) * 2000-03-06 2008-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2001257350A (ja) * 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4700160B2 (ja) 2000-03-13 2011-06-15 株式会社半導体エネルギー研究所 半導体装置
JP4118485B2 (ja) * 2000-03-13 2008-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4683688B2 (ja) 2000-03-16 2011-05-18 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
JP4393662B2 (ja) * 2000-03-17 2010-01-06 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
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JP4785229B2 (ja) 2000-05-09 2011-10-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
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KR100615579B1 (ko) 2004-09-20 2006-08-25 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 파워 라인 배치 방법
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JPS6136946A (ja) * 1984-07-30 1986-02-21 Nec Corp 半導体装置

Also Published As

Publication number Publication date
DE3785899D1 (de) 1993-06-24
JPH0324057B2 (ko) 1991-04-02
US4914503A (en) 1990-04-03
EP0259631B1 (en) 1993-05-19
JPS6344742A (ja) 1988-02-25
EP0259631A2 (en) 1988-03-16
DE3785899T2 (de) 1993-08-26
EP0259631A3 (en) 1988-12-14
KR910004617B1 (ko) 1991-07-08

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