KR950007059A - 집적 회로 - Google Patents

집적 회로 Download PDF

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KR950007059A
KR950007059A KR1019940018396A KR19940018396A KR950007059A KR 950007059 A KR950007059 A KR 950007059A KR 1019940018396 A KR1019940018396 A KR 1019940018396A KR 19940018396 A KR19940018396 A KR 19940018396A KR 950007059 A KR950007059 A KR 950007059A
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metal layer
bond pads
active element
substrate
integrated circuit
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KR1019940018396A
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KR0146013B1 (ko
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치티페디 사이리쉬
토마스 코크란 윌리엄
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리차드 디. 로먼
에이티 앤드 티 코포레이션
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Publication of KR950007059A publication Critical patent/KR950007059A/ko
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Publication of KR0146013B1 publication Critical patent/KR0146013B1/ko

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    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Abstract

능동 회로가 적어도 3개의 금속 레벨(211, 215,219)을 갖는 집적 회로내의 본드 패드(3) 아래에 위치된다. 본드 패드 근처의 금속 레벨(215)은 버퍼처럼 동작하고, 용납할 수 없는 큰 누설 전류를 유도하는 유전체(213)내의 크랙 전파를 방지한다.

Description

집적 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 집적 회로의 일부분의 평면도.
제2도는 제1도에 도시된 본 발명에 따른 집적 회로의 일부분의 단면도.

Claims (7)

  1. 기판(201)과; 상기 기판(201)의 표면에 능동소자(203)와; 상기 능동소자(203)의 일부분 위에 실질적으로 존재하는 복수의 본드 패드(3)와; 상기 본드 패드(3)와 상기 기판(201)사이의 복수의 패턴화된 금속층(215)으로서, 적어도 상기 금속층(215)이 상기 능동 소자(203)중 적어도 하나위에 실질적으로 존재하는 상기 금속층(215)과; 상기 패턴화된 금속층(215)들을 서로간에 분리시키고 그리고 상기 금속층(215)들을 상기 본드 패드(3)로부터 또한 상기 능동소자(203)로부터 분리시키는 유전체물질(214, 213, 217) 및 ; 상기 본드 패드(3)로부터 상기 능동 소자(203)까지의 전기적인 연결(251, 255, 215)을 포함하는 것을 특징으로 하는 집적 회로.
  2. 제1항에 있어서, 상기 패턴화된 금속층(215)중 상기 적어도 하나가 상기 본드 패드(3)중 적어도 하나에 전기적으로 연결되는 것을 특징으로 하는 집적 회로.
  3. 제2항에 있어서, 상기 패턴화된 금속층(215)중 상기 적어도 하나가 상기 본드 패드(3)의 적어도 하나 아래에서 상기 능동 회로의 적어도 한 소자(203)에 전기적으로 연결되는 것을 특징으로 하는 집적 회로.
  4. 제1항에 있어서, 세개의 금속 레벨(211, 215, 219)을 갖는 것을 특징으로 하는 집적 회로.
  5. 제1항에 있어서, 적어도 4개의 금속 레벨(211, 215, 219)을 갖는 것을 특징으로 하는 집적 회로.
  6. 기판(201)과; 상기 기판(201)의 표면에 형성된 능동 소자(203)와; 복수의 본드 패드(3)로서, 상기 본드 패드(3)중 적어도 하나가 상기 능동소자(203)중 적어도 하나위에 실질적으로 존재하는 상기 본드 패드(3)와; 상기 복수의 본드 패드(3)와 상기 기판(201) 사이에 패턴화된 금속층(215)으로서, 상기 금속층(215)의 적어도 일부분이 상기 능동소자(201)의 적어도 일부분 위에 실질적으로 존재하는 상기 금속층(215)과; 상기 패턴화된 금속층(215) 패드(3)로부터 상기 능동 소자 (203)까지의 전기적인 연결(251, 255, 215)을 포함하는 것을 특징으로 하는 집적회로.
  7. 제6항에 있어서, 상기 패턴화된 금속층(215)과 상기 능동소자(203)사이에 금속층(211)을 포함하고, 상기 금속층(211)은 유전체 물질(213)에 의해 상기 능동 소자(203) 및 상기 패턴화된 금속층(215)으로 분리되는 것을 특징으로 하는 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940018396A 1993-08-05 1994-07-28 집적 회로 KR0146013B1 (ko)

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US10243493A 1993-08-05 1993-08-05
US102,434 1993-08-05

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KR0146013B1 KR0146013B1 (ko) 1998-11-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100398729C (zh) * 2002-07-05 2008-07-02 乐金电子(天津)电器有限公司 全自动洗衣机离合器的电磁线圈结构

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3482779B2 (ja) 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
US6127245A (en) * 1997-02-04 2000-10-03 Micron Technology, Inc. Grinding technique for integrated circuits
EP0923126A1 (en) * 1997-12-05 1999-06-16 STMicroelectronics S.r.l. Integrated electronic device comprising a mechanical stress protection structure
KR100267105B1 (ko) * 1997-12-09 2000-11-01 윤종용 다층패드를구비한반도체소자및그제조방법
US6329712B1 (en) * 1998-03-25 2001-12-11 Micron Technology, Inc. High density flip chip memory arrays
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6087732A (en) 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
DE19845064A1 (de) * 1998-09-30 2000-04-13 Siemens Ag Halbleiterschaltkreis mit integrierter Selbsttestschaltung
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
JP2000183104A (ja) * 1998-12-15 2000-06-30 Texas Instr Inc <Ti> 集積回路上でボンディングするためのシステム及び方法
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
DE19908188A1 (de) * 1999-02-25 2000-09-07 Siemens Ag Verfahren zum Herstellen einer integrierten elektronischen Schaltung und integrierte elektronische Schaltung
US6486051B1 (en) * 1999-03-17 2002-11-26 Intel Corporation Method for relieving bond stress in an under-bond-pad resistor
JP2000269293A (ja) * 1999-03-18 2000-09-29 Fujitsu Ltd 半導体装置
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
US6372621B1 (en) * 1999-04-19 2002-04-16 United Microelectronics Corp. Method of forming a bonding pad on a semiconductor chip
JP2001007149A (ja) * 1999-06-24 2001-01-12 Nec Corp 高出力半導体装置
US6503820B1 (en) * 1999-10-04 2003-01-07 Koninklijke Philips Electronics N.V. Die pad crack absorption system and method for integrated circuit chip fabrication
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6838769B1 (en) * 1999-12-16 2005-01-04 Agere Systems Inc. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
US6417087B1 (en) 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
JP3727220B2 (ja) 2000-04-03 2005-12-14 Necエレクトロニクス株式会社 半導体装置
US6395568B1 (en) * 2000-07-25 2002-05-28 Advanced Micro Devices, Inc. Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products
TW531867B (en) * 2000-10-13 2003-05-11 Texas Instruments Inc Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface
DE10231385B4 (de) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
JP2003031579A (ja) * 2001-07-18 2003-01-31 Denso Corp センサ及びその製造方法
DE10229493B4 (de) * 2002-07-01 2007-03-29 Infineon Technologies Ag Integrierte Halbleiterstruktur
US20040036131A1 (en) * 2002-08-23 2004-02-26 Micron Technology, Inc. Electrostatic discharge protection devices having transistors with textured surfaces
DE10249192A1 (de) * 2002-10-22 2004-05-13 Infineon Technologies Ag Elektronisches Bauelement mit integriertem passiven elektronischen Bauelement und Verfahren zu dessen Herstellung
EP1563537B1 (en) * 2002-11-08 2008-04-09 Nxp B.V. Integrated circuit with at least one bump
JP4258205B2 (ja) * 2002-11-11 2009-04-30 パナソニック株式会社 半導体装置
US7495343B1 (en) 2003-07-31 2009-02-24 Nvidia Corporation Pad over active circuit system and method with frame support structure
US7453158B2 (en) * 2003-07-31 2008-11-18 Nvidia Corporation Pad over active circuit system and method with meshed support structure
US7038280B2 (en) * 2003-10-28 2006-05-02 Analog Devices, Inc. Integrated circuit bond pad structures and methods of making
US7429703B2 (en) * 2003-11-26 2008-09-30 Agere Systems Inc. Methods and apparatus for integrated circuit device power distribution via internal wire bonds
US6998335B2 (en) * 2003-12-13 2006-02-14 Chartered Semiconductor Manufacturing, Ltd Structure and method for fabricating a bond pad structure
US20050151265A1 (en) 2004-01-14 2005-07-14 Nian Yang Efficient use of wafer area with device under the pad approach
US7629689B2 (en) * 2004-01-22 2009-12-08 Kawasaki Microelectronics, Inc. Semiconductor integrated circuit having connection pads over active elements
JP4257526B2 (ja) * 2004-06-01 2009-04-22 セイコーエプソン株式会社 半導体装置
US7274108B2 (en) * 2004-11-15 2007-09-25 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits
CN100362657C (zh) * 2004-12-22 2008-01-16 中芯国际集成电路制造(上海)有限公司 半导体集成电路的内连焊盘
US7241636B2 (en) * 2005-01-11 2007-07-10 Freescale Semiconductor, Inc. Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US7247552B2 (en) * 2005-01-11 2007-07-24 Freescale Semiconductor, Inc. Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
JP4094012B2 (ja) * 2005-02-21 2008-06-04 松下電器産業株式会社 半導体装置
US7250311B2 (en) * 2005-02-23 2007-07-31 International Business Machines Corporation Wirebond crack sensor for low-k die
US20070001984A1 (en) * 2005-06-30 2007-01-04 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010336B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4186970B2 (ja) * 2005-06-30 2008-11-26 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010335B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4151688B2 (ja) * 2005-06-30 2008-09-17 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4761880B2 (ja) * 2005-08-09 2011-08-31 パナソニック株式会社 半導体装置
JP5066836B2 (ja) * 2005-08-11 2012-11-07 セイコーエプソン株式会社 電気光学装置及び電子機器
JP4671814B2 (ja) * 2005-09-02 2011-04-20 パナソニック株式会社 半導体装置
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
US8624346B2 (en) 2005-10-11 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Exclusion zone for stress-sensitive circuit design
US8552560B2 (en) * 2005-11-18 2013-10-08 Lsi Corporation Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing
FR2894716A1 (fr) * 2005-12-09 2007-06-15 St Microelectronics Sa Puce de circuits integres a plots externes et procede de fabrication d'une telle puce
US20070200233A1 (en) * 2005-12-14 2007-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structures with reduced coupling noise
JP4586739B2 (ja) * 2006-02-10 2010-11-24 セイコーエプソン株式会社 半導体集積回路及び電子機器
JP4072697B2 (ja) 2006-05-02 2008-04-09 セイコーエプソン株式会社 半導体装置
US7808117B2 (en) * 2006-05-16 2010-10-05 Freescale Semiconductor, Inc. Integrated circuit having pads and input/output (I/O) cells
US20070267748A1 (en) * 2006-05-16 2007-11-22 Tran Tu-Anh N Integrated circuit having pads and input/output (i/o) cells
US7271485B1 (en) 2006-09-11 2007-09-18 Agere Systems Inc. Systems and methods for distributing I/O in a semiconductor device
US7646078B2 (en) * 2007-01-17 2010-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Die saw crack stopper
US7952167B2 (en) * 2007-04-27 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line layout design
US8125052B2 (en) * 2007-05-14 2012-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure with improved cracking protection
DE102007046556A1 (de) * 2007-09-28 2009-04-02 Infineon Technologies Austria Ag Halbleiterbauelement mit Kupfermetallisierungen
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
JP5329068B2 (ja) * 2007-10-22 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置
EP2195837A1 (en) * 2007-10-31 2010-06-16 Agere Systems Inc. Bond pad support structure for semiconductor device
US8643147B2 (en) * 2007-11-01 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with improved cracking protection and reduced problems
US8334582B2 (en) * 2008-06-26 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protective seal ring for preventing die-saw induced stress
US7906836B2 (en) * 2008-11-14 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US8368180B2 (en) * 2009-02-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line metal structure
CN101996993A (zh) * 2009-08-13 2011-03-30 中芯国际集成电路制造(上海)有限公司 利用单一金属化的焊盘下的器件
JP5485132B2 (ja) * 2010-12-28 2014-05-07 パナソニック株式会社 半導体装置
ITMI20111370A1 (it) 2011-07-22 2013-01-23 St Microelectronics Srl Piazzola di contatto
US20130154099A1 (en) 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
JP5926988B2 (ja) * 2012-03-08 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US20210134744A1 (en) * 2019-11-05 2021-05-06 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US11239164B2 (en) * 2020-02-26 2022-02-01 Nanya Technology Corporation Semiconductor device with metal plug having rounded top surface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921034A (ja) * 1982-07-27 1984-02-02 Toshiba Corp 半導体装置
JPS6164147A (ja) * 1984-09-05 1986-04-02 Nec Corp 半導体装置
JPS63283040A (ja) * 1987-05-15 1988-11-18 Toshiba Corp 半導体装置
JP2522837B2 (ja) * 1989-09-19 1996-08-07 富士通株式会社 ウエハ・スケ―ル半導体装置
JP3432284B2 (ja) * 1994-07-04 2003-08-04 三菱電機株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100398729C (zh) * 2002-07-05 2008-07-02 乐金电子(天津)电器有限公司 全自动洗衣机离合器的电磁线圈结构

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