JPS5921034A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5921034A
JPS5921034A JP57129563A JP12956382A JPS5921034A JP S5921034 A JPS5921034 A JP S5921034A JP 57129563 A JP57129563 A JP 57129563A JP 12956382 A JP12956382 A JP 12956382A JP S5921034 A JPS5921034 A JP S5921034A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
pad
silicon layer
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57129563A
Other languages
English (en)
Inventor
Masayasu Abe
正泰 安部
Masaharu Aoyama
青山　正治
Takashi Yasujima
安島　隆
Toshio Yonezawa
敏夫 米沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57129563A priority Critical patent/JPS5921034A/ja
Priority to EP83107397A priority patent/EP0100100B1/en
Priority to DE8383107397T priority patent/DE3376926D1/de
Publication of JPS5921034A publication Critical patent/JPS5921034A/ja
Priority to US06/837,663 priority patent/US4636832A/en
Pending legal-status Critical Current

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  • Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置にかかり、特に半導体装置ｔこお
ける半導体チップのポンディングパッドの改良構造に関
する。
〔発明の技術的背景〕
半導体チップがその主面ｌこ備えるポンディングパッド
部分の従来の構造を第１図に示す。図において、（１）
は層厚が約１．０μｍのアルミニウムで形成されたポン
ディングパッドで、層厚が約１０μｍの５ｉｏｔで形成
された電気絶縁層（２）に被着形成されている。また、
前記電気絶縁層が上面に形成されているＮ型半導体のエ
ピタキシャル層（３）には、前記パッド下の領域を電気
的に分離するためにこの領域を囲むリング状のＰ型拡散
領域（４）があり、ボンディング加工時の衝撃で電気絶
縁層ｌこ亀裂を生ずることがあってもリーク電流を阻止
するようになっている。
〔背景技術の問題点〕
斜上の背景技術には次にあげる問題点がある。
まず、ポンディングパッド領域を電気的に分離するため
に拡散領域（例えば第１図に示すＰ型拡散領域（４））
を設ける必要がある。この分離領域は少くとも幅１０μ
ｍ程度は要するので、半導体装置の最大の急務である微
細化に重大な障害になる。
次に、ボンディングによるダメージは半導体チップのＰ
Ｎ接合にまで及ぶことが多く電流のリーク対策は完全で
はない。
さらにポンディングパッド下の領域（一般に而積層２０
０００μＩ）には素子（トランジスタ、ダイオード、抵
抗、配線等）を作れない。これは菓子上にホンディング
ができないためで、素子チップの面積利用率を低下させ
る欠点がある。
〔発明の目的〕
この発明は斜上の従来の欠点に鑑み半導体チップにおけ
るポンディングパッド部の改良構造を提供するものであ
る。
〔発明の概要〕
この発明ｌこかかる半導体装置は半導体チップがその主
面にポンディングパッドを備え、このパッドにボンディ
ングを施してなるものにおいて、パッドが直接または電
気絶縁層を介してこのパッドとほぼ等しい寸法の多結晶
シリコン層または非晶質シリコン層に被着形成されてい
ることを特徴とする。
〔発明の実施例Ｊ 次にこの発明を１実施例につき図面を参照して詳細に説
明する。半導体チップのポンディングパッド部を示す第
２図において、アルミニウムのポンディングパッド（１
）の下には層厚０．３μｍの５ＩＯ２層（１１）の電気
絶縁層を介して層厚０．４μｍの多結晶シリコン層（１
２１が設けられている。また、上記多結晶シリコン層よ
り下層の構造はこの多結晶シリコン層に密着させて層厚
０．６μｍのＰ２Ｏ層（１３、さらに層厚１０μｍのア
ルミニウム配線層ａ力、層厚０．６１ｚｍの５ｉ０２層
（ｌωの順に積層してＮ型エピタキシャル層（３）に至
る構造となっている。
ここで、上記多結晶シリコン層（１２＋はプラズマＣＶ
Ｄ法によって形成し、その条件は温度３８０℃。
プラズマ出力２００ＷにてガスはＳ目−■４を用いガス
圧をＩ　Ｘ　１０−’Ｐａで好適した。また、ＰＳＧ層
０３１は常圧ＣＶＤ法にて、リンの濃度をＩ　Ｘ　ｌ　
Ｏ”ａｔｏｍ／ｃＩｎ”になるように制御して形成した
。
次にボンディングバンド（１）は−例の１００μｍ口、
層厚１０μｍに形成し、これに線径２５μｍφの金のホ
ンディングワイヤＯＱをボンディングした。ボンディン
グにはボンディングワイヤ端に形成したボールを３２５
°０に加熱し、パッドへの押圧力を４０〜６０ノにして
良好なボンディング強度が得られた。
なお、−Ｆ記多結晶シリコン層に代わって電子ビーム蒸
着法、あるいはＡｒイオンスパッタ法によって非晶質シ
リコンを被着し、パターニングを施すことによっても斜
上と同様の構造と効果を得ることができた。
〔発明の効果〕
この発明により５ば、金属のポンディングパッドの下に
直接あるいは電気絶縁層を介して多結晶シリコンあるい
は非晶質シリコン層を配置することによって、引張強さ
が４ル／ｌｌｌｌＩ２程度の５ｉ０２層に７〜３５　Ｋ
ｐ／ｍＮの多結晶シリコン層、または非晶質シリコン質
をもって補強し、亀裂の発生を極減した。この多結晶シ
リコン層の効果を調査するため、第２図に示された構造
で多結晶シリコン層が設けられた場合と、設けられない
場合とのＮＰＮ　）ランジスタのコレクターベース問お
よびエミッターベース間のリーク電流を評価した結果を
第３図に示す。図にみられるように、金ボールのパッド
への押圧力が増加すると衝撃が大きくなりＮＰＮ　）ラ
ンジスタの接合部にダメージを生じ、リーク電流が増大
する。多結晶シリコン層が無い場合、抑圧力４０１でリ
ークが発生するので良好なホンディングが行なえる領域
の４０〜７０Ｆ領域では基板上のトランジスタが破壊さ
れていることになる。これに対し本発明の多結晶シリコ
ン層が設けられている場合ｊとは押圧力が１４０　ｙ　
ｉでリークが発生せず、基板上の素子に影響せずに任意
の位置にポンディングパッドを設けることが可能になる
などの顕著な効果がある。
【図面の簡単な説明】
第１図は素子チップにおける従来のポンディングパッド
部の断面図、第２図は１実施例のポンディングパッド部
の断面図、第３図はこの発明によりボンディングのダメ
ージを阻止できることをＮＰＮトランジスタの接合部の
リーク電流値で示す線図である。 １　　　　　ポンディングパッド １１．１５　　　５ｉｆｔ層（電気絶縁層）１２　　　
　　　多結晶シリコン層 １　：（Ｐ　Ｓ　０層 １４　　　　　　アルミ、−ウム配線層代理人　弁理士
　井・上　−男 第　　１　図 第　　２　図 第　　３

Claims (1)

    【特許請求の範囲】
  1. 半導体チップがその主面にポンディングパッドを備え、
    このパッドにボンディングを施してなる半導体装置にお
    いて、ポンデイングパットカ直接または電気絶縁層を介
    してこのパッドとほぼ等しい寸法の多結晶シリコン層ま
    たは非晶質シリコン層に被着形成されていることを特徴
    とする半導体装置。
JP57129563A 1982-07-27 1982-07-27 半導体装置 Pending JPS5921034A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57129563A JPS5921034A (ja) 1982-07-27 1982-07-27 半導体装置
EP83107397A EP0100100B1 (en) 1982-07-27 1983-07-27 Semiconductor device with an improved bonding section
DE8383107397T DE3376926D1 (en) 1982-07-27 1983-07-27 Semiconductor device with an improved bonding section
US06/837,663 US4636832A (en) 1982-07-27 1986-03-04 Semiconductor device with an improved bonding section

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57129563A JPS5921034A (ja) 1982-07-27 1982-07-27 半導体装置

Publications (1)

Publication Number Publication Date
JPS5921034A true JPS5921034A (ja) 1984-02-02

Family

ID=15012578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57129563A Pending JPS5921034A (ja) 1982-07-27 1982-07-27 半導体装置

Country Status (4)

Country Link
US (1) US4636832A (ja)
EP (1) EP0100100B1 (ja)
JP (1) JPS5921034A (ja)
DE (1) DE3376926D1 (ja)

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Also Published As

Publication number Publication date
US4636832A (en) 1987-01-13
EP0100100A2 (en) 1984-02-08
EP0100100B1 (en) 1988-06-01
EP0100100A3 (en) 1985-07-31
DE3376926D1 (en) 1988-07-07

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