CN100362657C - 半导体集成电路的内连焊盘 - Google Patents

半导体集成电路的内连焊盘 Download PDF

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CN100362657C
CN100362657C CNB2004100934667A CN200410093466A CN100362657C CN 100362657 C CN100362657 C CN 100362657C CN B2004100934667 A CNB2004100934667 A CN B2004100934667A CN 200410093466 A CN200410093466 A CN 200410093466A CN 100362657 C CN100362657 C CN 100362657C
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metal level
metal
layer
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bonding pads
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CN1797756A (zh
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俞大立
刘志纲
宁先捷
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

半导体集成电路的内连焊盘，焊盘包括：六层金属层(M1-M6)，分别设置在相邻金属层之间的多层介质层；和设置在发明焊盘的最底层金属层(M1)和顶层金属层(M6)之间金属电路(2)；其特征是，焊盘最底层金属层(M1)和顶层金属层(M6)的尺寸与焊盘的整体尺寸相同，最底层金属层(M1)和顶层金属层(M6)之间镶嵌类似于金属-介质-金属(MIM)结构的无源装置，无源装置的金属层不连续，无源装置的金属层图形随着电路图形变化而变化。

Description

半导体集成电路的内连焊盘
技术领域
本发明总的涉及半导体集成电路的焊盘，具体涉及半导体集成电路的内连焊盘。
背景技术
焊盘是半导体集成电路中的重要构成部分，具有至少三层的集成电路中，有源电路位于焊盘下面，邻近焊盘层的金属层起分散应力的缓冲作用，防止焊盘与位于其下的电路之间出现漏电流。
通常半导体集成电路包括；衬底；衬底表面上形成的多个有源器件；多个有源器件中的一部分上顺序形成的具有底部掩盖层(footprint)的焊盘；位于焊盘与衬底之间的具有底部掩盖层(footprint)的已构图的金属层，已构图的金属层顺序形成在多个有源器件上，每层金属层与有源器件用第一电介质材料电隔开，焊盘的底部掩盖层顺序重叠在已构图的金属层的底部掩盖层上；每层已构图的金属层与焊盘用第二电介质材料隔开，每层已构图的金属层在第一电介质材料与有源器件之间形成阻挡层，已防止第二电介质材料与有源器件之间产生漏电流；和将焊盘连接到有源器件的电连接线。
1998年5月12日公布的美国专利US-No.5751065，发明名称是：“具有焊盘下面的有源器件的集成电路”中公开了一种集成电路结构，从该美国专利中可以清楚地看到焊盘与集成电路其他另部件之间的关系。集成电路包括：集成电路芯片1；形成子集成电路上的多个金属焊盘3；介质层，覆盖在集成电路芯片1的整个表面上，介质层构图露出金属焊盘3；集成电路具有位于焊盘3下面例如I/O缓冲器的有源器件；至少一层已构图的金属层覆盖位于焊盘下的和有源器件区上面的部分。最接近焊盘的金属层起到分散应力的作用，使介质层的整体性在焊接过程中不被破坏，甚至在焊接过程中焊盘与其最接近的金属层之间的介质损坏时，漏电流也会在金属层终止。所以，焊盘下面的区域可以用于有源器件。
但是，半导体集成电路中常规的焊盘包括多层金属层，例如，包括六层金属层。有源电路位于焊盘下面。全部焊盘位于半导体集成电路的非有源区上，现有的焊盘中包括的多层金属层的布图从下到上完全一致，如图1显示的；金属电路位于焊盘与衬底之间如图2显示的。因此，按现有的焊盘布图结构造成半导体集成电路的总体布图困难，造成半导体集成电路的裸芯面积大，集成度低。
为了克服现有技术中存在的缺点，提出本发明。
发明内容
本发明的目的是提供一种半导体集成电路内连用的焊盘。基本上克服了限于技术中的缺点。
按本发明的焊盘，包括：多层金属层，分别设置在相邻金属层之间的多层介质层，和设置在焊盘最底层金属层与顶层金属层之间的金属电路。焊盘最底层金属层和顶层金属层尺寸与焊盘的整体尺寸相同，焊盘最底层金属层和顶层金属层之间镶嵌类似于金属-介质-金属(MIM)结构的无源装置。无源装置的金属层不连续，无源装置金属层图形随着电路图形变化而变化。焊盘最底层金属层起到分散应力的作用，使位于金属层之间的介质层的整体性在焊接过程中不被破坏，甚至在焊接过程中焊盘与其最接近的金属层之间的介质损坏时，漏电流也会在金属层终止，焊盘的最底层金属层保护器件在封装过程中不被损坏。焊盘顶层金属层通过不在有源器件上的链路电连接，以防止损坏器件。
由于按本发明的焊盘的中间金属层布图随着电路布图设计的需要变化，因此，增加了布图的灵活性，使布图设计容易。此外还减小了半导体集成电路裸芯的面积，提高了半导体集成电路的集成度，降低了半导体集成电路的生产成本。
附图说明
通过结合附图进行的以下描述可以更好地理解本发明目的和本发明的优点，附图是说明书的一个组成部分，附图与说明书的文字部分一起说明本发明的原理和特征，附图中显示出代表本发明原理和特征的实施例。全部附图中相同的部分用相同的参考数字或符号指示。附图中：
图1是现有的焊盘剖视图，全部焊盘都在非有源区上；
图2是显示现有的焊盘与衬底之间的金属电路布图结构的剖视图；
图3是显示按本发明一个实施例的焊盘下面和焊盘之间的有源器件和电路的布图结构的剖视图；和
图4是显示按本发明另一个实施例的焊盘下面和焊盘之间的有源器件和电路的布图结构的剖视图。
附图中的参考数字指示的部件说明：
1-焊盘；2-电路；3-焊点；4-接点；P Well-P阱；M1-M6-金属层1-金属层6；
具体实施方式
[实施例1]
图3是显示按本发明一个实施例的焊盘下面和焊盘之间的有源器件和电路的布图结构的剖视图。
参见图3，按本发明的焊盘位于有源器件上，本发明焊盘包括：六层金属层M1-M6，分别设置在相邻金属层之间的多层介质层；和设置在发明焊盘的最底层的金属层1即附图标记M1所指结构和顶层的金属层6即附图标记M6所指结构之间金属电路2。本发明焊盘的最底层金属层1即附图标记M1所指结构和顶层金属层6即附图标记M6所指结构的尺寸与焊盘的整体尺寸相同，焊盘最底层金属层1即附图标记M1所指结构和顶层金属层6即附图标记M6所指结构之间镶嵌类似于金属-介质-金属(MIM)结构的无源装置，无源装置的金属层不连续，无源装置的金属层图形随着电路图形变化而变化；焊盘底层金属层1即附图标记M1所指结构起到分散应力的作用，使位于金属层之间的介质层的整体性在焊接过程中不被破坏，甚至在焊接过程中焊盘与其最接近的金属层之间的介质损坏时，漏电流也会在金属层终止。焊盘底层金属层1即附图标记M1所指结构保护器件在封装过程中不被损坏。焊盘顶层金属层6即附图标记M6所指结构，通过链路电连接，其中该链路不在有源器件上的，以防止损坏器件。焊盘底层金属层1即附图标记M1所指结构与焊盘顶层金属层6即附图标记M6所指结构的焊盘结构取决于金属电路的布图结构。
[实施例2]
图4是显示按本发明另一个实施例的焊盘下面和焊盘之间的有源器件和电路的布图结构的剖视图。
按本实施例的焊盘，底层金属层1即附图标记M1所指结构和顶层金属层6即附图标记M6所指结构与第一实施例相同，只是底层金属层1即附图标记M1所指结构和顶层金属层6即附图标记M6所指结构之间的结构与第一实施例不同，这种差别是由底层金属层1即附图标记M1所指结构和顶层金属层6即附图标记M6所指结构之间的电路结构决定的。
由于按本发明的焊盘的底层金属层1即附图标记M1所指结构与顶层金属层6即附图标记M6所指结构之间的金属层布图随着电路布图设计的需要变化，因此，增加了布图的灵活性，使布图设计容易。此外，还减小了半导体集成电路裸芯的面积，提高了半导体集成电路的集成度，降低了半导体集成电路的生产成本。
以上详细描述了按本发明的半导体集成电路的内连焊盘。但是本发明不限于本文中的详细描述。本行业的技术人员应了解，在不脱离本发明的精神和范围的前提下，本发明能以其他的形式实施，本发明还有各种改进和变化，这些改进和变化都落入本发明要求保护的范围内。因此，按本发明的全部技术方案，所列举的实施方式只是用于说明本发明而不是限制本发明，并且，本发明不局限于本文中描述的细节。本发明要求保护的范围由所附的权利要求书界定。

Claims (1)

1.半导体集成电路的内连焊盘，该内连焊盘包括：六层金属层(M1-M6)，分别设置在相邻金属层之间的多层介质层；和设置在该内连焊盘的最底层的金属层1(M1)和顶层的金属层6(M6)之间的金属电路(2)其特征是，焊盘最底层的金属层1(M1)和顶层的金属层6(M6)的尺寸与该内联焊盘的整体尺寸相同，最底层的金属层1(M1)和顶层的金属层6(M6)之间镶嵌金属-介质-金属(MIM)结构的无源装置，该无源装置的金属层不连续，该无源装置的金属层图形随着电路图形的变化而变化；该内连焊盘最底层的金属层1(M1)起到分散应力的作用，使位于金属层之间的介质层的整体性在焊接过程中不被破坏，甚至在焊接过程中焊盘与其最接近的金属层之间的介质损坏时，漏电流也会在金属层终止，该内连焊盘底层的金属层1(M1)保护器件在封装过程中不被损坏；该内连焊盘顶层的金属层6(M6)通过链路电连接，其中，所述链路不在有源器件上，以防止损坏器件。
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US7821038B2 (en) * 2008-03-21 2010-10-26 Mediatek Inc. Power and ground routing of integrated circuit devices with improved IR drop and chip performance
US8624391B2 (en) * 2009-10-08 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip design with robust corner bumps
KR101190744B1 (ko) * 2010-05-27 2012-10-12 에스케이하이닉스 주식회사 멀티칩 구조를 가지는 반도체 집적 회로

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US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
JP2000031415A (ja) * 1998-07-15 2000-01-28 Hitachi Ltd 半導体装置およびその製造方法
US20020053740A1 (en) * 2000-05-04 2002-05-09 Stamper Anthony K. Recessed bond pad
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
JP2000031415A (ja) * 1998-07-15 2000-01-28 Hitachi Ltd 半導体装置およびその製造方法
US20020053740A1 (en) * 2000-05-04 2002-05-09 Stamper Anthony K. Recessed bond pad
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells

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