JP2007128990A - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP2007128990A JP2007128990A JP2005318933A JP2005318933A JP2007128990A JP 2007128990 A JP2007128990 A JP 2007128990A JP 2005318933 A JP2005318933 A JP 2005318933A JP 2005318933 A JP2005318933 A JP 2005318933A JP 2007128990 A JP2007128990 A JP 2007128990A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 152
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000007789 sealing Methods 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 23
- 230000006870 function Effects 0.000 claims description 15
- 229910001111 Fine metal Inorganic materials 0.000 claims description 6
- 230000009131 signaling function Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 238000000926 separation method Methods 0.000 description 4
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】半導体素子1と、4方向に配置された電極2および電極2を有する面の裏面に外部電極4を有し半導体素子1を搭載するインターポーザ5と、半導体素子1をインターポーザ5に固定する接着材料6と、半導体素子1に有する電極とインターポーザ5が有する電極2を電気的に接続する金属細線7と、半導体素子1と金属細線7を包含する領域を封止する絶縁材料8と、外部電極4に搭載した金属ボール9から構成され、インターポーザ5上に4方向配置された電極2で囲われた領域内のコーナー対角にパターン10を設ける。
【選択図】図1
Description
今後、BGAは更なる低コスト化が要求され、図7に示すような一枚の基板17における半導体装置の取れ数が多くなるインターポーザ設計をすることが重要となる。一枚の基板17における半導体装置の取れ数を多くするためには、インターポーザを有効的に、半導体装置化されない無駄なスペースを省くことが必須である。
その結果、従来から4方向に配置された電極で囲まれていた領域に、電極から引き出した配線を各層に接続するためのプラグを配置しているが、グランド機能を有する配線を配置しないため、プラグ配置に対し設計自由度が向上する。
(実施の形態1)
本発明の実施の形態1の半導体装置を説明する。
(実施の形態2)
本発明の実施の形態2の半導体装置を説明する。
(実施の形態3)
本発明の実施の形態3の半導体装置を説明する。
(実施の形態4)
本発明の実施の形態4の半導体装置を説明する。
(実施の形態5)
本発明の実施の形態5の半導体装置を説明する。
(製造方法)
本発明の実施の形態の半導体装置の製造方法を説明する。
2 (インターポーザが有する)電極
3 (インターポーザが有する電極から引き出される)配線
4 (インターポーザに配置された)受けランド
5 インターポーザ
6 接着材料
7 金属細線
8 絶縁材料
9 金属ボール
10 (4方向に配置された電極に囲われた領域内に配置された)パターン
11 ¬状(かぎ状)パターン
12 線幅を太く設計したパターン
13 分離パターン
14 分離パターン
15 パターン兼受けランド
16 (インターポーザが有する電極から引き出された)配線
17 基板
18 (4方向に配置された電極に囲われた領域外に配置された)認識パターン
Claims (6)
- 複数の電極を有する半導体素子と、基板の表面に4方向に配置された電極および前記基板の裏面に配置された外部電極を有し、前記半導体素子を前記基板の表面側に搭載するインターポーザと、前記半導体素子を前記インターポーザに固定する接着材料と、前記半導体素子が有する前記複数の電極と前記インターポーザが有する前記4方向に配置された電極とを電気的に接続する金属細線と、前記半導体素子と前記金属細線とを包含する領域を封止する絶縁材料と、前記インターポーザが有する前記外部電極に搭載した金属ボールとで構成し、前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に、前記4方向に配置された電極と異なる形状のパターンを少なくとも一対設けたことを特徴とする半導体装置。
- 前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に設けた前記パターンは、¬状(かぎ状)に形成したことを特徴とする請求項1記載の半導体装置。
- 前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に設けた前記パターンは、グランド機能を有し、前記半導体素子と前記金属細線で電気的に接続したことを特徴とする請求項1記載の半導体装置。
- 前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に設けた前記パターンは、前記半導体素子が有する信号機能を持つ電極と前記金属細線で電気的に接続したことを特徴とする請求項1記載の半導体装置。
- 前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に設けた前記パターンは、前記インターポーザ上で前記4方向に配置された電極から引き出された配線と各層の配線とをつなぐプラグに接続される受けランド機能を持たせたことを特徴とする請求項1記載の半導体装置。
- 複数の電極を有する半導体素子を、基板の表面に4方向に配置された電極および前記基板の裏面に配置された外部電極を有するインターポーザの前記表面側に搭載する工程と、前記半導体素子が有する前記複数の電極と前記インターポーザが有する前記4方向に配置された電極とを金属細線で電気的に接続する工程と、前記半導体素子と前記金属細線とを包含する領域を絶縁材料により封止する工程と、前記金属ボールを前記インターポーザが有する前記外部電極に搭載する工程と、前記半導体素子をインターポーザの前記表面側に搭載した状態で、前記半導体素子ごとに半導体装置として個片化する工程とを有し、前記半導体素子を前記インターポーザに搭載する工程で、前記インターポーザ上で前記4方向に配置された電極で囲われた領域内のコーナー対角に設けた前記パターンを、前記インターポーザ上の位置を認識するための認識マークとして用いてアライメントすることを特徴とする半導体装置の製造方法。
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JP2005318933A JP4744269B2 (ja) | 2005-11-02 | 2005-11-02 | 半導体装置とその製造方法 |
CNB2006101285371A CN100565861C (zh) | 2005-11-02 | 2006-08-30 | 半导体器件及其制造方法 |
US11/543,153 US7485960B2 (en) | 2005-11-02 | 2006-10-05 | Semiconductor device and manufacturing method thereof |
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JP4378387B2 (ja) * | 2007-02-27 | 2009-12-02 | Okiセミコンダクタ株式会社 | 半導体パッケージ及びその製造方法 |
US20140070404A1 (en) * | 2012-09-12 | 2014-03-13 | Shing-Ren Sheu | Semiconductor package structure and interposer therefor |
Citations (7)
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JPS5793148A (en) * | 1980-12-03 | 1982-06-10 | Dainippon Printing Co Ltd | Printing system of musical characters |
JPS6477943A (en) * | 1987-09-18 | 1989-03-23 | Ibiden Co Ltd | Substrate for mounting electronic component |
JPH027536A (ja) * | 1988-06-27 | 1990-01-11 | Nec Corp | 半導体装置 |
JPH07297221A (ja) * | 1994-04-25 | 1995-11-10 | Matsushita Electric Works Ltd | 半導体パッケージ |
JP2002246400A (ja) * | 2001-02-19 | 2002-08-30 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003234372A (ja) * | 2002-01-31 | 2003-08-22 | Stmicroelectronics Inc | 集積回路基板上に集積回路ダイを整合させるシステム及び方法 |
JP2004356650A (ja) * | 2004-08-16 | 2004-12-16 | Oki Electric Ind Co Ltd | 半導体装置 |
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JPS6035249Y2 (ja) * | 1980-11-27 | 1985-10-19 | 日本電気株式会社 | 半導体装置用回路基板 |
BR9403529A (pt) * | 1993-01-14 | 1999-06-15 | Weissenfluh Hawe Neos | Pasta de dentes |
PL180991B1 (pl) * | 1994-09-21 | 2001-05-31 | Unilever Nv | Doustna kompozycja czyszcząca |
DE60001366T2 (de) * | 1999-06-04 | 2003-07-03 | Unilever N.V., Rotterdam | Orale zusammensetzung enthaltend perlit |
US6432387B1 (en) * | 2000-03-23 | 2002-08-13 | Create Co., Ltd. | Ionic tooth polishing agent |
US6720644B2 (en) * | 2000-10-10 | 2004-04-13 | Sony Corporation | Semiconductor device using interposer substrate and manufacturing method therefor |
WO2002082540A1 (fr) * | 2001-03-30 | 2002-10-17 | Fujitsu Limited | Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6877992B2 (en) * | 2002-11-01 | 2005-04-12 | Airborn, Inc. | Area array connector having stacked contacts for improved current carrying capacity |
US6992380B2 (en) * | 2003-08-29 | 2006-01-31 | Texas Instruments Incorporated | Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area |
JP2005109145A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | 半導体装置 |
-
2005
- 2005-11-02 JP JP2005318933A patent/JP4744269B2/ja active Active
-
2006
- 2006-08-30 CN CNB2006101285371A patent/CN100565861C/zh not_active Expired - Fee Related
- 2006-10-05 US US11/543,153 patent/US7485960B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS5793148A (en) * | 1980-12-03 | 1982-06-10 | Dainippon Printing Co Ltd | Printing system of musical characters |
JPS6477943A (en) * | 1987-09-18 | 1989-03-23 | Ibiden Co Ltd | Substrate for mounting electronic component |
JPH027536A (ja) * | 1988-06-27 | 1990-01-11 | Nec Corp | 半導体装置 |
JPH07297221A (ja) * | 1994-04-25 | 1995-11-10 | Matsushita Electric Works Ltd | 半導体パッケージ |
JP2002246400A (ja) * | 2001-02-19 | 2002-08-30 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003234372A (ja) * | 2002-01-31 | 2003-08-22 | Stmicroelectronics Inc | 集積回路基板上に集積回路ダイを整合させるシステム及び方法 |
JP2004356650A (ja) * | 2004-08-16 | 2004-12-16 | Oki Electric Ind Co Ltd | 半導体装置 |
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US20070096314A1 (en) | 2007-05-03 |
CN100565861C (zh) | 2009-12-02 |
JP4744269B2 (ja) | 2011-08-10 |
US7485960B2 (en) | 2009-02-03 |
CN1959973A (zh) | 2007-05-09 |
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