KR960035835A - 반도체장치와 그 제조방법 - Google Patents
반도체장치와 그 제조방법 Download PDFInfo
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- KR960035835A KR960035835A KR1019960006004A KR19960006004A KR960035835A KR 960035835 A KR960035835 A KR 960035835A KR 1019960006004 A KR1019960006004 A KR 1019960006004A KR 19960006004 A KR19960006004 A KR 19960006004A KR 960035835 A KR960035835 A KR 960035835A
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- semiconductor device
- interlayer insulating
- insulating layer
- forming
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Abstract
본 발명은 복수의 패드를 가지는 반도체소자를 포함하는 반도체장치와 그 제조방법에 관한 것이며, 복수의 패드를 가지는 반도체소자의 패드형성면에, 패드중의 하나에 도통하는 배선부가 복수 형성되고, 배선부위 소정 위치상에 범프가 복수 형성되어 이루어진다. 따라서, 반도체소자와 회로기판과의 선팽창계수의 차에 기인하는 문제를 해소하여 충분한 신뢰성을 확보하는 동시에, 플립칩화에 의한 고밀도화의 효과를 충분히 발휘할 수 있고, 또한 코스트업을 억제할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도~제2c도는 본 발명의 반도체장치의 일실시예의 개략구성을 나타낸 도면.
Claims (3)
- 복수의 패드를 가지는 반도체소자의 패드형성면에, 상기 패드중의 하나에 도통하는 배선부가 복수형성되고, 이 배선부의 소정 위치상에 범프가 복수 형성되어 이루어지는 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 상기 범프는 2개의 군으로 분류되고, 상기 패드중의 신호핀으로 될 패드에 도통하는 군의 범프가 상기 패드형성면의 주변부에 배설되고, 상기 패드중의 전원핀으로 될 패드에 도통하는 다른 군의 범프가 상기 패드형성면의 내측에 배설되어 이루어지는 것을 특징으로 하는 반도체 장치.
- 패드를 가지는 반도체소자상에, 회로기판과 전기적·기계적으로 접속되는 범프를 형성하는 반도체 장치의 제조방법으로서, 상기 반도체소자상에 제1의 층간절연층을 형성하고, 또한 이 제1 층간절연층의, 상기 패드의 지상부를 개구하여 이 패드를 노출시키는 제1공정과, 상기 제1의 층간절연층상에, 상기 패드로부터 반도체소자상의 범프형성위치까지 연장된 패턴의 배선부를 형성하는 제2공정과, 상기 배선부를 덮어서 상기 제1의 층간절연층상에 제2의 층간절연층을 형성하고, 또한 이 제2의 층간절연층의, 상기 범프형성위치의 직상부에 개구하여 상기 배선부를 노출시키는 제3공정과, 상기 반도체소자의, 제2의 층간절연층을 형성한 측의 면에 도전층을 형성하는 제4공정과, 상기 도전층상에 도금레지스트층을 형성하고, 또한 상기 범프형성위치의 직상부를 개구하여 상기 도전층을 노출시키는 제5공정과, 상기 반도체소자의 도금레지스트층측을 전해액중에 침지하고, 통전함으로써 상기 범프형성위치의 직상부에 범프를 형성하는 제6공정을 가지는 것을 특징으로 하는 반도체장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1995-49353 | 1995-03-09 | ||
JP4935395A JP3362545B2 (ja) | 1995-03-09 | 1995-03-09 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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KR960035835A true KR960035835A (ko) | 1996-10-28 |
KR100403691B1 KR100403691B1 (ko) | 2004-01-07 |
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ID=12828662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019960006004A KR100403691B1 (ko) | 1995-03-09 | 1996-03-08 | 반도체장치와그제조방법 |
Country Status (3)
Country | Link |
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US (2) | US6008543A (ko) |
JP (1) | JP3362545B2 (ko) |
KR (1) | KR100403691B1 (ko) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6741085B1 (en) | 1993-11-16 | 2004-05-25 | Formfactor, Inc. | Contact carriers (tiles) for populating larger substrates with spring contacts |
US6690185B1 (en) | 1997-01-15 | 2004-02-10 | Formfactor, Inc. | Large contactor with multiple, aligned contactor units |
TW448524B (en) | 1997-01-17 | 2001-08-01 | Seiko Epson Corp | Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment |
US6215184B1 (en) * | 1998-02-19 | 2001-04-10 | Texas Instruments Incorporated | Optimized circuit design layout for high performance ball grid array packages |
JP3335575B2 (ja) | 1997-06-06 | 2002-10-21 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US6317333B1 (en) * | 1997-08-28 | 2001-11-13 | Mitsubishi Denki Kabushiki Kaisha | Package construction of semiconductor device |
US6169022B1 (en) * | 1997-10-13 | 2001-01-02 | Fujitsu Limited | Method of forming projection electrodes |
US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
JP3768817B2 (ja) * | 1997-10-30 | 2006-04-19 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP3654485B2 (ja) * | 1997-12-26 | 2005-06-02 | 富士通株式会社 | 半導体装置の製造方法 |
KR100551607B1 (ko) * | 1998-01-19 | 2006-02-13 | 시티즌 도케이 가부시키가이샤 | 반도체 패키지 |
JP3715816B2 (ja) * | 1999-02-18 | 2005-11-16 | ローム株式会社 | 半導体チップ |
JP3727172B2 (ja) * | 1998-06-09 | 2005-12-14 | 沖電気工業株式会社 | 半導体装置 |
US6162718A (en) * | 1998-09-04 | 2000-12-19 | Advanced Micro Devices | High speed bump plating/forming |
JP2000100814A (ja) | 1998-09-18 | 2000-04-07 | Hitachi Ltd | 半導体装置 |
JP4564113B2 (ja) * | 1998-11-30 | 2010-10-20 | 株式会社東芝 | 微粒子膜形成方法 |
JP3577419B2 (ja) * | 1998-12-17 | 2004-10-13 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
EP1176637A4 (en) | 1999-01-22 | 2006-09-13 | Hitachi Ltd | INTEGRATED SEMICONDUCTOR CIRCUIT AND MANUFACTURE THEREOF |
KR100687548B1 (ko) * | 1999-01-27 | 2007-02-27 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 웨이퍼 제조 방법, 반도체 장치 제조 방법 및 칩 사이즈의 반도체 웨이퍼 패키지 제조 방법 |
US6251694B1 (en) * | 1999-05-26 | 2001-06-26 | United Microelectronics Corp. | Method of testing and packaging a semiconductor chip |
US7215131B1 (en) | 1999-06-07 | 2007-05-08 | Formfactor, Inc. | Segmented contactor |
US6150729A (en) * | 1999-07-01 | 2000-11-21 | Lsi Logic Corporation | Routing density enhancement for semiconductor BGA packages and printed wiring boards |
JP3610262B2 (ja) * | 1999-07-22 | 2005-01-12 | 新光電気工業株式会社 | 多層回路基板及び半導体装置 |
JP2010192928A (ja) * | 1999-08-12 | 2010-09-02 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
US6483190B1 (en) * | 1999-10-20 | 2002-11-19 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
US6365973B1 (en) * | 1999-12-07 | 2002-04-02 | Intel Corporation | Filled solder |
DE60109339T2 (de) * | 2000-03-24 | 2006-01-12 | Texas Instruments Incorporated, Dallas | Verfahren zum Drahtbonden |
JP2001339047A (ja) * | 2000-05-29 | 2001-12-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
TW577152B (en) | 2000-12-18 | 2004-02-21 | Hitachi Ltd | Semiconductor integrated circuit device |
JP2007335888A (ja) * | 2000-12-18 | 2007-12-27 | Renesas Technology Corp | 半導体集積回路装置 |
US6445069B1 (en) * | 2001-01-22 | 2002-09-03 | Flip Chip Technologies, L.L.C. | Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor |
US6605525B2 (en) * | 2001-05-01 | 2003-08-12 | Industrial Technologies Research Institute | Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed |
US7115986B2 (en) | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
JP3534717B2 (ja) * | 2001-05-28 | 2004-06-07 | シャープ株式会社 | 半導体装置の製造方法 |
KR100412133B1 (ko) * | 2001-06-12 | 2003-12-31 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 칩크기 패키지 및 그의 제조방법 |
KR100567225B1 (ko) * | 2001-07-10 | 2006-04-04 | 삼성전자주식회사 | 칩 패드가 셀 영역 위에 형성된 집적회로 칩과 그 제조방법 및 멀티 칩 패키지 |
DE10231385B4 (de) * | 2001-07-10 | 2007-02-22 | Samsung Electronics Co., Ltd., Suwon | Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung |
SG122743A1 (en) | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
TW536765B (en) * | 2001-10-19 | 2003-06-11 | Acer Labs Inc | Chip package structure for array type bounding pad |
JP4154219B2 (ja) * | 2001-12-25 | 2008-09-24 | キヤノン株式会社 | 湿式ガス処理方法 |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
JP2003243538A (ja) | 2002-02-12 | 2003-08-29 | Hitachi Ltd | 半導体集積回路装置 |
US6975035B2 (en) | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
SG115455A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
SG115459A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
US20040036170A1 (en) | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US7498666B2 (en) * | 2004-09-27 | 2009-03-03 | Nokia Corporation | Stacked integrated circuit |
KR100642643B1 (ko) * | 2005-03-18 | 2006-11-10 | 삼성전자주식회사 | 내부회로의 전원/접지선들과 직접 접속되는 재배치된전원/접지선들을 갖는 반도체 칩들 및 그 제조방법들 |
JP4726679B2 (ja) * | 2006-03-31 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体試験方法および半導体装置 |
US8592977B2 (en) * | 2006-06-28 | 2013-11-26 | Megit Acquisition Corp. | Integrated circuit (IC) chip and method for fabricating the same |
US7749885B2 (en) * | 2006-12-15 | 2010-07-06 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers |
JP2010062170A (ja) * | 2008-09-01 | 2010-03-18 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP5285385B2 (ja) * | 2008-10-15 | 2013-09-11 | 株式会社フジクラ | 積層配線基板の製造方法 |
TWI429039B (zh) * | 2010-10-21 | 2014-03-01 | Via Tech Inc | 積體電路晶片封裝及實體層介面排列 |
CN102110666B (zh) * | 2010-11-23 | 2012-12-12 | 威盛电子股份有限公司 | 集成电路芯片封装及实体层介面排列 |
JP2012129570A (ja) * | 2012-04-03 | 2012-07-05 | Megica Corp | チップの製造方法 |
KR102357937B1 (ko) | 2015-08-26 | 2022-02-04 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
KR102372349B1 (ko) | 2015-08-26 | 2022-03-11 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4087314A (en) * | 1976-09-13 | 1978-05-02 | Motorola, Inc. | Bonding pedestals for semiconductor devices |
JPS62150728A (ja) * | 1985-12-25 | 1987-07-04 | Hitachi Ltd | テ−プキヤリアおよびそれを用いた半導体装置 |
JPS6378555A (ja) * | 1986-09-20 | 1988-04-08 | Fujitsu Ltd | 半導体装置 |
US5066831A (en) * | 1987-10-23 | 1991-11-19 | Honeywell Inc. | Universal semiconductor chip package |
US5220199A (en) * | 1988-09-13 | 1993-06-15 | Hitachi, Ltd. | Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate |
US4994902A (en) * | 1988-11-30 | 1991-02-19 | Hitachi, Ltd. | Semiconductor devices and electronic system incorporating them |
US5036163A (en) * | 1989-10-13 | 1991-07-30 | Honeywell Inc. | Universal semiconductor chip package |
US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
JPH03250628A (ja) * | 1990-02-28 | 1991-11-08 | Hitachi Ltd | 半導体装置 |
JPH04346231A (ja) * | 1991-05-23 | 1992-12-02 | Canon Inc | 半導体装置の製造方法 |
JPH07502377A (ja) * | 1991-12-18 | 1995-03-09 | クロスポイント・ソルーションズ・インコーポレイテッド | フィールドプログラマブルゲートアレイのための拡張アーキテクチャ |
US5281684A (en) * | 1992-04-30 | 1994-01-25 | Motorola, Inc. | Solder bumping of integrated circuit die |
KR960016007B1 (ko) * | 1993-02-08 | 1996-11-25 | 삼성전자 주식회사 | 반도체 칩 범프의 제조방법 |
JP3057130B2 (ja) * | 1993-02-18 | 2000-06-26 | 三菱電機株式会社 | 樹脂封止型半導体パッケージおよびその製造方法 |
KR960004093B1 (ko) * | 1993-03-17 | 1996-03-26 | 금성일렉트론주식회사 | 반도체소자의 범프형성방법 |
US5442852A (en) * | 1993-10-26 | 1995-08-22 | Pacific Microelectronics Corporation | Method of fabricating solder ball array |
US5490040A (en) * | 1993-12-22 | 1996-02-06 | International Business Machines Corporation | Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array |
US5641988A (en) * | 1993-12-22 | 1997-06-24 | Vlsi Technology, Inc. | Multi-layered, integrated circuit package having reduced parasitic noise characteristics |
US5506756A (en) * | 1994-01-25 | 1996-04-09 | Intel Corporation | Tape BGA package die-up/die down |
JP3238011B2 (ja) * | 1994-07-27 | 2001-12-10 | 株式会社東芝 | 半導体装置 |
JP3142723B2 (ja) * | 1994-09-21 | 2001-03-07 | シャープ株式会社 | 半導体装置及びその製造方法 |
US5534465A (en) * | 1995-01-10 | 1996-07-09 | At&T Corp. | Method for making multichip circuits using active semiconductor substrates |
US5661082A (en) * | 1995-01-20 | 1997-08-26 | Motorola, Inc. | Process for forming a semiconductor device having a bond pad |
US5851911A (en) * | 1996-03-07 | 1998-12-22 | Micron Technology, Inc. | Mask repattern process |
US5736456A (en) * | 1996-03-07 | 1998-04-07 | Micron Technology, Inc. | Method of forming conductive bumps on die for flip chip applications |
US5903058A (en) * | 1996-07-17 | 1999-05-11 | Micron Technology, Inc. | Conductive bumps on die for flip chip application |
-
1995
- 1995-03-09 JP JP4935395A patent/JP3362545B2/ja not_active Expired - Fee Related
-
1996
- 1996-03-05 US US08/611,494 patent/US6008543A/en not_active Expired - Fee Related
- 1996-03-08 KR KR1019960006004A patent/KR100403691B1/ko not_active IP Right Cessation
-
1997
- 1997-06-27 US US08/885,757 patent/US6030890A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3362545B2 (ja) | 2003-01-07 |
KR100403691B1 (ko) | 2004-01-07 |
US6008543A (en) | 1999-12-28 |
JPH08250498A (ja) | 1996-09-27 |
US6030890A (en) | 2000-02-29 |
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