JP5285385B2 - 積層配線基板の製造方法 - Google Patents
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 14
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- 239000010931 gold Substances 0.000 claims description 8
- 239000011368 organic material Substances 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
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- BVKZGUZCCUSVTD-UHFFFAOYSA-N carbonic acid Chemical compound OC(O)=O BVKZGUZCCUSVTD-UHFFFAOYSA-N 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
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- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明に係る積層配線基板の製造方法において、前記保護導電層は、ニッケル、金、銀、白金、錫、パラジウム及びこれらの合金の中から選択される少なくとも一つを含むことを特徴とする。
本発明に係る積層配線基板の製造方法において、前記再配線層は銅めっき層により形成され、前記有機絶縁膜は感光性有機材料を素材として形成されていることを特徴とする。
に示す工程では、例えばポリイミド樹脂フィルムからなるフレキシブルな第1絶縁基板1aの一方の面(上面)に銅箔製の配線材料層1Bが設けられた片面銅張板(CCL)を用意する。前記第1絶縁基板1a及び配線材料層1Bにはそれぞれ厚さ25μm及び12μmのものを使用した。
1a、1d、2a、4a 絶縁基板
1b、1f、2b、4b、4c、 配線層
1c、1g、2c、 貫通電極
2 第2基板材
3 半導体素子
3a 半導体基板
3b 電極パツト
3c 無機絶縁膜
3d 再配線層
3f 有機絶縁膜
3g 保護導電層
4 第3基板材
5 接着層材5
5a、5b、 接着層
Claims (3)
- 対面配置された第1基板材と第2基板材との間に半導体素子を内蔵して接着封止した積層配線基板の製造方法であって、
前記半導体素子を形成する段階は、
(A−1)複数の半導体素子に対応する複数の素子領域を半導体ウエハ表面に設けて前記各素子領域毎に電極パッドを形成し、前記電極パッドに対する第1コンタクト孔を有する無機絶縁膜を前記ウエハ表面に形成する工程と、
(A−2)前記第1コンタクト孔を通じて前記電極パッドに接続された再配線層を前記無機絶縁膜上に形成する工程と、
(A−3)前記無機絶縁膜及び前記再配線層を覆って、前記ウエハ上に感光性有機材料膜を形成する工程と、
(A−4)前記感光性有機材料膜にフォトリソグラフィを施して前記再配線層に対する第2コンタクト孔を開けて焼成処理することによって、第2コンタクト孔を有する有機絶縁膜を前記ウエハ表面に形成する工程と、
(A−5)前記第2コンタクト孔内にて前記再配線層表面を保護導電層で被覆する工程と、
(A−6)各素子領域に対するウエハ検査後、ダイシングを行って各素子領域に対応して個片化された各半導体素子を取り出す工程とを有し、
前記第1基板材と第2基板材との間に半導体素子を内蔵して接着封止する段階は、
(B)絶縁基板の一方の面にパターニングされた配線層、他方の面に形成された接着層、及び前記絶縁基板及び接着層を貫通し一端面が前記配線層に接続され他端面が前記接着層の下面側に突出した状態で露出され、前記半導体素子の再配線層上の保護導電層に対応する導電性ペーストからなる貫通電極を有する第1基板材を用意する工程と、
(C)前記貫通電極の前記他端面を前記半導体素子の再配線層及び保護導電層に位置合わせして押し付け接続すると共に、前記貫通電極と前記再配線層及び前記保護導電層の低抵抗接続及び前記半導体素子の損傷回避が得られるように前記貫通電極の突出高さを調整して押圧力を調整し、前記半導体素子を前記接着層に仮止め接着して前記第1基板材と一体化する工程と、
(D)前記第1基板材に対面させる第2基板材を提供する工程と、
(E)前記第1基板材と一体化された前記半導体素子を前記第2基板材上に位置合わせして重ね合わせる工程と、
(F)前記第1基板材と前記第2基板材とを重ね合わせ方向に一括加熱プレスし、前記接着層により前記半導体素子を囲み前記第1及び第2基板材を相互接着する工程と、
を有し、
前記第1基板材に設けた前記貫通電極は、前記絶縁基板の前記他方の面に前記接着層と樹脂フィルムを順次重ねて貼り合わせ、前記絶縁基板、前記接着層及び前記樹脂フィルムを前記他方の面側から貫通する貫通孔を形成し、前記貫通孔に前記導電性ペーストを充填し、前記樹脂フィルムを剥離して形成され、
前記樹脂フィルムの厚さを選定することにより、前記第1基板材に設けた前記貫通電極の突出高さを調整することを特徴とする積層配線基板の製造方法。 - 前記保護導電層は、ニッケル、金、銀、白金、錫、パラジウム及びこれらの合金の中から選択される少なくとも一つを含むことを特徴とする請求項1に記載の積層配線基板の製造方法。
- 前記再配線層は銅めっき層により形成され、前記有機絶縁膜は感光性有機材料を素材として形成されていることを特徴とする請求項1または請求項2に記載の積層配線基板の製造方法。
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EP2865005A4 (en) | 2012-06-25 | 2016-03-30 | Res Triangle Inst Int | THREE-DIMENSIONAL ELECTRONIC HOUSING USING ADHESIVE LAYER WITHOUT PATTERN |
US9881905B2 (en) | 2014-04-21 | 2018-01-30 | Research Triangle Institute | Electronic packages with three-dimensional conductive planes, and methods for fabrication |
JP6712764B2 (ja) | 2015-05-25 | 2020-06-24 | パナソニックIpマネジメント株式会社 | 伸縮性フレキシブル基板およびその製造方法 |
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JP3362545B2 (ja) * | 1995-03-09 | 2003-01-07 | ソニー株式会社 | 半導体装置の製造方法 |
JP3563635B2 (ja) * | 1999-04-21 | 2004-09-08 | 株式会社東芝 | 半導体集積回路装置およびその製造方法 |
JP2005039017A (ja) * | 2003-07-18 | 2005-02-10 | Hitachi Ltd | 半導体装置の製造方法および配線基板の製造方法 |
EP1951015A4 (en) * | 2005-10-14 | 2011-03-23 | Fujikura Ltd | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD |
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