KR880013241A - 다중칩 모듈 구조체 - Google Patents

다중칩 모듈 구조체 Download PDF

Info

Publication number
KR880013241A
KR880013241A KR1019880003559A KR880003559A KR880013241A KR 880013241 A KR880013241 A KR 880013241A KR 1019880003559 A KR1019880003559 A KR 1019880003559A KR 880003559 A KR880003559 A KR 880003559A KR 880013241 A KR880013241 A KR 880013241A
Authority
KR
South Korea
Prior art keywords
pins
wiring board
wiring
layer
same
Prior art date
Application number
KR1019880003559A
Other languages
English (en)
Other versions
KR910001422B1 (ko
Inventor
다카지 다케나카
도시타다 네츠
시기히데카
마사카즈 야마모토
Original Assignee
원본미기재
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 원본미기재, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 원본미기재
Publication of KR880013241A publication Critical patent/KR880013241A/ko
Application granted granted Critical
Publication of KR910001422B1 publication Critical patent/KR910001422B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

내용 없음

Description

다중칩 모듈 구조체
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 일실시예에 따름 다중칩 모듈구조체가 도시된 사시도, 제 2 도는 제 1 도에 도시된 다중칩 모듈 구조체의 평면도, 제 3 도는 제 2 도의 선Ⅲ-Ⅲ의 부분 단면도.

Claims (3)

  1. 서로 반대측에 위치하는 제 1 및 제조표면을 가지는 세라믹 다중층 배선반과, 상기 제 1 표면상에 다수의 반도체장치를 장착시키기 위해 이 제 1 표면상에 배열된 다수의 접속패드와, 상기 제2표면상에 배열되고, 다수의 전원I/O핀과 다수의 신호 I/O핀을 포함하는 다수의 I/O핀으로 구성되는 핀 격자 배열 타입의 다중칩 모듈 구조체에 있어서, 상기 배선반에 지지된 동일 타입의 반도체장치 각각에 대해 동일 크기의 다수의 배선반영역이 각각 배설되고, 상기 접속 패드 및 I/O핀의 배열구조가 동일 크기의 각 배선 반영역마다 동일하게 되어 있고, 동일하게 배열된 상기 접속패드와 동일하게 배열된 상기 I/O 핀간의 위치관계가 동일 크기의 각 배선 반영역내에서 일정하게 되어 있고, 상기 전원 I/O 핀에 접속될 상기 배선반내의 급속화 패턴이 동일 타입의 각 반도체장치마다 일정하게 되는 것을 특징으로 하는 다중칩 모듈 구조체.
  2. 제 1 항에 있어서, 상기 전원 I/O핀은 전압 I/O핀과 접지 I/O핀으로 구성되는것을 특징으로 하는 다중칩 모듈 구조체.
  3. 제 1 항에 있어서, 상기 배선반은, 상기 반도체장치를 장착시키기 위하여 상기 접속 패드가 배설되는 상부층과, 상기 접속패드의 격자피치를 상기 배선반 내측의 관통구멍의 격차피치로 전환시키기 위한 팽창층과, 상기 반도체장치간의 국부적인 배선을 이루기 위한 팽창층과, 상기 반도체장치간의 국부적인 배선을 이루기 위한 다수의 신호배선층과, 이 신호 배선층 사이에 위치하고, 전압을 공급하도록 그리고 상기 신호 배선층상의 신호 컨덕터의 특성 임퍼던스가 조화를 이루도록 작용하는 금속화 패턴을 가지는 전원층과, 상기 배선반내의 상기 관통구멍의 격자피치를 I/O 핀의 격자 피치로 전환시키기 위한 전환층과, 상기 I/O핀에 접속시키기 위한 패드를 가지는 하부층을 포함하는 것을 특징으로 하는 다중칩 모듈구조체.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880003559A 1987-04-01 1988-03-31 다중칩 모듈 구조체 KR910001422B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-077518 1987-04-01
JP62077518A JPS63245952A (ja) 1987-04-01 1987-04-01 マルチチップモジュ−ル構造体
JP62-77518 1987-04-01

Publications (2)

Publication Number Publication Date
KR880013241A true KR880013241A (ko) 1988-11-30
KR910001422B1 KR910001422B1 (ko) 1991-03-05

Family

ID=13636186

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003559A KR910001422B1 (ko) 1987-04-01 1988-03-31 다중칩 모듈 구조체

Country Status (4)

Country Link
US (1) US4930002A (ko)
EP (1) EP0285064A3 (ko)
JP (1) JPS63245952A (ko)
KR (1) KR910001422B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100341077B1 (en) * 1998-12-31 2002-09-27 Simm Tech Co Ltd Structure of multi-layered module in pcb

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
JP2507476B2 (ja) * 1987-09-28 1996-06-12 株式会社東芝 半導体集積回路装置
US4926241A (en) * 1988-02-19 1990-05-15 Microelectronics And Computer Technology Corporation Flip substrate for chip mount
FR2634340B1 (fr) * 1988-07-13 1994-06-17 Thomson Csf Dispositif d'interconnexion entre un circuit integre et un circuit electrique, application du dispositif a la connexion d'un circuit integre notamment a un circuit imprime, et procede de fabrication du dispositif
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
JP2978511B2 (ja) * 1989-09-20 1999-11-15 株式会社日立製作所 集積回路素子実装構造体
US5157477A (en) * 1990-01-10 1992-10-20 International Business Machines Corporation Matched impedance vertical conductors in multilevel dielectric laminated wiring
JPH0716100B2 (ja) * 1990-01-10 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層配線モジュール
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
DE59105080D1 (de) * 1990-05-28 1995-05-11 Siemens Ag IC-Gehäuse, bestehend aus drei beschichteten dielektrischen Platten.
JP2960560B2 (ja) * 1991-02-28 1999-10-06 株式会社日立製作所 超小型電子機器
EP0516866A1 (en) * 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
JP2960276B2 (ja) * 1992-07-30 1999-10-06 株式会社東芝 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
DE69330450T2 (de) * 1992-08-05 2001-11-08 Fujitsu Ltd., Kawasaki Dreidimensionaler Multichipmodul
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
JP3228589B2 (ja) * 1993-03-15 2001-11-12 株式会社東芝 マルチチップモジュール
US5391914A (en) * 1994-03-16 1995-02-21 The United States Of America As Represented By The Secretary Of The Navy Diamond multilayer multichip module substrate
US5544174A (en) * 1994-03-17 1996-08-06 The United States Of America As Represented By The Secretary Of The Air Force Programmable boundary scan and input output parameter device for testing integrated circuits
JP3412942B2 (ja) * 1995-01-11 2003-06-03 株式会社東芝 半導体装置
DE19507547C2 (de) * 1995-03-03 1997-12-11 Siemens Ag Verfahren zur Montage von Chips
TW299564B (ko) * 1995-10-04 1997-03-01 Ibm
US5691569A (en) * 1995-12-20 1997-11-25 Intel Corporation Integrated circuit package that has a plurality of staggered pins
US5825628A (en) * 1996-10-03 1998-10-20 International Business Machines Corporation Electronic package with enhanced pad design
JP3063687B2 (ja) * 1997-06-30 2000-07-12 日本電気株式会社 マルチチップモジュール
US6111756A (en) * 1998-09-11 2000-08-29 Fujitsu Limited Universal multichip interconnect systems
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ，半導体チップ群及びマルチチップモジュール
KR100734290B1 (ko) 2005-11-28 2007-07-02 삼성전자주식회사 출력 채널이 공유되는 테스트 패드를 구비하는 필름형반도체 패키지 및 필름형 반도체 패키지의 테스트 방법,테스트 채널이 공유되는 패턴을 구비하는 테스트 장치 및반도체 장치 그리고 반도체 장치에서의 테스트 방법
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US11647582B1 (en) 2020-08-26 2023-05-09 Ian Getreu Rapid implementation of high-temperature analog interface electronics

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231154A (en) * 1979-01-10 1980-11-04 International Business Machines Corporation Electronic package assembly method
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS5818951A (ja) * 1981-07-22 1983-02-03 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体チツプ装着用基板
US4602271A (en) * 1981-07-22 1986-07-22 International Business Machines Corporation Personalizable masterslice substrate for semiconductor chips
JPS6014494A (ja) * 1983-07-04 1985-01-25 株式会社日立製作所 セラミツク多層配線基板およびその製造方法
JPS6022396A (ja) * 1983-07-19 1985-02-04 日本電気株式会社 回路基板
US4649417A (en) * 1983-09-22 1987-03-10 International Business Machines Corporation Multiple voltage integrated circuit packaging substrate
JPS6124255A (ja) * 1984-07-13 1986-02-01 Hitachi Ltd 半導体パツケ−ジ構造
JPS6127667A (ja) * 1984-07-17 1986-02-07 Mitsubishi Electric Corp 半導体装置
JPS621258A (ja) * 1985-06-26 1987-01-07 Nec Corp マルチチツプパツケ−ジ
US4811082A (en) * 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100341077B1 (en) * 1998-12-31 2002-09-27 Simm Tech Co Ltd Structure of multi-layered module in pcb

Also Published As

Publication number Publication date
JPS63245952A (ja) 1988-10-13
KR910001422B1 (ko) 1991-03-05
EP0285064A2 (en) 1988-10-05
EP0285064A3 (en) 1989-08-02
US4930002A (en) 1990-05-29

Similar Documents

Publication Publication Date Title
KR880013241A (ko) 다중칩 모듈 구조체
KR960035835A (ko) 반도체장치와 그 제조방법
KR930011201A (ko) 반도체 장치
KR100281813B1 (ko) 열및전기적으로개선된볼그리드패키지
JP4592122B2 (ja) パッケージ層の数を削減したフリップチップ・パッケージ
KR960006982B1 (ko) 계단형 다층 상호 연결 장치
KR910004076A (ko) 후막 박막 적층 기판 및 그것을 사용한 전자회로 장치
KR940003010A (ko) 다층 배선 기판, 이 기판을 이용한 반도체 장치 및 다층 배선 기판의 제조방법
KR960032693A (ko) 반도체장치 및 그 본딩패드 구조
KR920010853A (ko) 수지봉지형 반도체장치
KR900005576A (ko) 반도체 집적회로 장치
KR940008109A (ko) 반도체집적회로장치
KR950007059A (ko) 집적 회로
KR970030718A (ko) 반도체 패키지를 위한 패드 및 쓰루홀 배열구조
KR930001361A (ko) 플립 칩 실장 및 결선 패키지 및 그 방법
KR870004507A (ko) 수지봉지형 반도체 장치
KR920010872A (ko) 멀티칩 모듈
ATE125395T1 (de) Gitterartige steckerstift-anordnung für einen paketförmigen integrierten schaltkreis.
DE3482719D1 (de) Halbleiterelement und herstellungsverfahren.
KR920000208A (ko) 실장기판
KR970703617A (ko) 전도선을 가진 리드프레임 리드를 포함한 고밀도 집적회로 조립체(a high density integrated circuit assembly combining leadframe leads with conductive traces)
KR920022431A (ko) 반도체 장치용 패키지
KR920001697A (ko) 수직형 반도체 상호 접촉 방법 및 그 구조
KR940006187Y1 (ko) 반도체장치
KR890015403A (ko) 반도체집적회로장치

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010118

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee