KR920000208A - 실장기판 - Google Patents

실장기판 Download PDF

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Publication number
KR920000208A
KR920000208A KR1019910002945A KR910002945A KR920000208A KR 920000208 A KR920000208 A KR 920000208A KR 1019910002945 A KR1019910002945 A KR 1019910002945A KR 910002945 A KR910002945 A KR 910002945A KR 920000208 A KR920000208 A KR 920000208A
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KR
South Korea
Prior art keywords
wiring
layer
unit
mounting board
board according
Prior art date
Application number
KR1019910002945A
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English (en)
Other versions
KR0157060B1 (ko
Inventor
구니오 미야자끼
유다까 스기다
아끼오 무고오
타다히꼬 미요시
오사무 미우라
아끼오 다까하시
슈니찌 누마다
사또루 오기와라
가즈지 야마다
히로가즈 이노우에
후미유끼 고바야시
Original Assignee
미다 가쓰시게
가부시기가이샤 하다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미다 가쓰시게, 가부시기가이샤 하다찌 세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR920000208A publication Critical patent/KR920000208A/ko
Application granted granted Critical
Publication of KR0157060B1 publication Critical patent/KR0157060B1/ko

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0379—Stacked conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies

Abstract

내용 없음

Description

실장기판
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본발명의 실장기판의 단면도,
제2도는 동과 폴리이미드를 사용한 4층으로 이루어지는 배선 유닛을 작성하는 방법을 나타낸도,
제3도는 배선 유닛간의 접속방법을 나타낸도이다.

Claims (9)

  1. 세라믹 또는 실리콘 기판상에 다층의 박막 배선부를 가지는 실장기판에 있어서, 상기 박막 배선부가 목수의 배선층으로 이루어지는 배선 유닛으로 분할되어 있고, 또 상기 유닛의 표면 도체층과 동일면내에 형성된 접합패드를 통하여 각 유닛간의 배선이 전기적으로 접속되는 구조를 가지는 실장기판.
  2. 제1장에 있어서, 상기 배선 유닛의 일부가 신호층과 전원층 및 접지층으로 구성되고, 상기 전원층 및 접지층이 야표면에 형성되고, 또 각층이 관통구멍에 의하여 전기적으로 접속되어 있는 것을 특징으로 하는 실장기판.
  3. 제2항에 있어서, 상기 배선 유닛의 전원층 및 접지층은 전면막이고, 그 전면막면내에 전면막과는 전기적으로 절열된 패드가 형성되어 있는 것을 특징으로 하는 실장기판.
  4. 제1항에 있어서, 상기 배선 유닛을 구성하는 배선층의 도체층이 동, 알루미늄, 금 또는 은 중 어느 하나의 금속으로 형성되어 있는 것을 특징으로 하는 실장기판.
  5. 제1항에 있어서, 상기 배선 유닛을 구성하는 배선층의 절연층이 폴리이미드로 형성되어 있는 것을 특징으로 하는 실장기판.
  6. 제1항에 있어서, 상기 배선 유닛에 있어서, 접속을 위하여 서로 대향하는 2개의 유닛표면의 도체 패턴의 형상이 동일한 것을 특징으로 하는 실장기판.
  7. 제1항에 있어서, 상기 배선 유닛간의 접합패드의 크기가 각 내층배선을 연결하기 위한 관통구멍의 크기보다도 큰 것을 특징으로 하는 실장기판.
  8. 제1항에 있어서, 상기 유닛은 상기 박막 배선의 구성요소와는 다른 가기판을 사용하여 형성되는 것을 특징으로 하는 실장기판.
  9. 제1항에 있어서, 상기유닛은 박막 프로세서에 의하여 상기 가기판상에 형성되는 것을 특징으로 하는 실장기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910002945A 1990-02-26 1991-02-23 실장기판 KR0157060B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2042468A JP2510747B2 (ja) 1990-02-26 1990-02-26 実装基板
JP90-42468 1990-02-26
JP90-042468 1990-02-26

Publications (2)

Publication Number Publication Date
KR920000208A true KR920000208A (ko) 1992-01-10
KR0157060B1 KR0157060B1 (ko) 1998-12-15

Family

ID=12636905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002945A KR0157060B1 (ko) 1990-02-26 1991-02-23 실장기판

Country Status (3)

Country Link
US (1) US5350886A (ko)
JP (1) JP2510747B2 (ko)
KR (1) KR0157060B1 (ko)

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EP0526133B1 (en) * 1991-07-26 1997-03-19 Nec Corporation Polyimide multilayer wiring substrate and method for manufacturing the same
JP2817530B2 (ja) * 1992-08-19 1998-10-30 日本電気株式会社 ポリイミド多層配線基板の製造方法
JPH0828580B2 (ja) * 1993-04-21 1996-03-21 日本電気株式会社 配線基板構造及びその製造方法
US5834705A (en) * 1994-03-04 1998-11-10 Silicon Graphics, Inc. Arrangement for modifying eletrical printed circuit boards
US6028364A (en) * 1994-09-20 2000-02-22 Hitachi, Ltd. Semiconductor device having a stress relieving mechanism
US6423571B2 (en) 1994-09-20 2002-07-23 Hitachi, Ltd. Method of making a semiconductor device having a stress relieving mechanism
US5663677A (en) * 1995-03-30 1997-09-02 Lucent Technologies Inc. Integrated circuit multi-level interconnection technique
JP2748890B2 (ja) * 1995-06-14 1998-05-13 日本電気株式会社 有機樹脂多層配線基板およびその製造方法
JP3112059B2 (ja) 1995-07-05 2000-11-27 株式会社日立製作所 薄膜多層配線基板及びその製法
JP2917867B2 (ja) * 1995-08-14 1999-07-12 日本電気株式会社 多層配線基板
JP2751902B2 (ja) * 1995-12-27 1998-05-18 日本電気株式会社 多層印刷配線板の製造方法
JP2002064270A (ja) * 2000-08-17 2002-02-28 Matsushita Electric Ind Co Ltd 回路基板とその製造方法
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JP3583396B2 (ja) * 2001-10-31 2004-11-04 富士通株式会社 半導体装置の製造方法、薄膜多層基板及びその製造方法
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JP5486376B2 (ja) 2010-03-31 2014-05-07 ルネサスエレクトロニクス株式会社 半導体装置
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US9147662B1 (en) * 2013-12-20 2015-09-29 Stats Chippac Ltd. Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof

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Also Published As

Publication number Publication date
JPH03246993A (ja) 1991-11-05
KR0157060B1 (ko) 1998-12-15
JP2510747B2 (ja) 1996-06-26
US5350886A (en) 1994-09-27

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