KR900019545A - 표면장착용 배선기판의 제조방법 - Google Patents

표면장착용 배선기판의 제조방법 Download PDF

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Publication number
KR900019545A
KR900019545A KR1019900007209A KR900007209A KR900019545A KR 900019545 A KR900019545 A KR 900019545A KR 1019900007209 A KR1019900007209 A KR 1019900007209A KR 900007209 A KR900007209 A KR 900007209A KR 900019545 A KR900019545 A KR 900019545A
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KR
South Korea
Prior art keywords
wiring board
manufacturing
surface mount
mount wiring
plating layer
Prior art date
Application number
KR1019900007209A
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English (en)
Other versions
KR920007120B1 (ko
Inventor
하루미 다시로
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900019545A publication Critical patent/KR900019545A/ko
Application granted granted Critical
Publication of KR920007120B1 publication Critical patent/KR920007120B1/ko

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

내용 없음

Description

평면장착용 배선기판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 배선기판의 제조방법에 다이패드와 본딩패드에 전해 Au도금을 수행한 다음 다이패드-본딩패드사이를 전기적으로 격절한 상태를 모식적으로 나타낸 평면도, 제2도는 본 발명에 따른 표면장착용 배선기판을 이용해서 구성한 하이브리드회로예를 나타낸 단면도이다.

Claims (1)

  1. 배선기판(5)의 소정영역면에 Cu 또는 Al로 이루어진 다이패드(1)와 본딩패드(2)의 최소한 어느 하나를 상호 전기적으로 접속해서 복수개 형성하는 공정과, 이 형성된 각 패드면상에 전해도금에 의해 Au도금층을 피복형성하는 공정 및, 이 Au도금층이 피복형성된 배선기판(5)의 필요한 영역을 선택적으로 절제하고 각 패드를 전기적으로 접속해 주는 도체를 절단해서 각 패드를 상호 전기적으로 격절시키는 공정을 구비해서 구성된 것을 특징으로 하는 표면장착용 배선기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900007209A 1989-05-22 1990-05-19 표면장착용 배선기판의 제조방법 KR920007120B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP89-128038 1989-05-22
JP1-128038 1989-05-22
JP1128038A JPH02306690A (ja) 1989-05-22 1989-05-22 表面実装用配線基板の製造方法

Publications (2)

Publication Number Publication Date
KR900019545A true KR900019545A (ko) 1990-12-24
KR920007120B1 KR920007120B1 (ko) 1992-08-24

Family

ID=14974977

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900007209A KR920007120B1 (ko) 1989-05-22 1990-05-19 표면장착용 배선기판의 제조방법

Country Status (5)

Country Link
US (1) US5042147A (ko)
EP (1) EP0399768B1 (ko)
JP (1) JPH02306690A (ko)
KR (1) KR920007120B1 (ko)
DE (1) DE69015879T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100389314B1 (ko) * 2001-07-18 2003-06-25 엘지전자 주식회사 도금인입선 없는 인쇄회로기판의 제조방법

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9202077L (sv) * 1992-07-06 1994-01-07 Ellemtel Utvecklings Ab Komponentmodul
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US5367763A (en) * 1993-09-30 1994-11-29 Atmel Corporation TAB testing of area array interconnected chips
KR0145768B1 (ko) * 1994-08-16 1998-08-01 김광호 리드 프레임과 그를 이용한 반도체 패키지 제조방법
WO1997011588A1 (en) 1995-09-18 1997-03-27 Tessera, Inc. Microelectronic lead structures with dielectric layers
US5724717A (en) * 1996-08-09 1998-03-10 The Whitaker Corporation Method of making an electrical article
JPH11135898A (ja) * 1997-10-31 1999-05-21 Asahi Optical Co Ltd プリント配線基板
JP3468179B2 (ja) * 1999-11-25 2003-11-17 株式会社村田製作所 表面実装部品
JP4484444B2 (ja) * 2003-04-11 2010-06-16 三洋電機株式会社 回路装置の製造方法
JP2013030712A (ja) * 2011-07-29 2013-02-07 Toshiba Corp 半導体モジュールおよび半導体モジュールの製造方法
US10754439B2 (en) * 2018-06-29 2020-08-25 Intel Corporation Selectively displaced keys for input and output

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483570A (ko) * 1965-06-23 1967-09-06
US3614832A (en) * 1966-03-09 1971-10-26 Ibm Decal connectors and methods of forming decal connections to solid state devices
NL7101602A (ko) * 1971-02-05 1972-08-08
US3781596A (en) * 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US3996603A (en) * 1974-10-18 1976-12-07 Motorola, Inc. RF power semiconductor package and method of manufacture
JPS5559795A (en) * 1978-10-30 1980-05-06 Nippon Electric Co Printed circuit board and method of manufacturing same
JPS5822767B2 (ja) * 1978-12-29 1983-05-11 富士ゼロックス株式会社 和文タイプライタ
DE3430290A1 (de) * 1984-08-17 1986-02-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur selektiven metallisierung
DE3704547A1 (de) * 1987-02-13 1988-08-25 Bbc Brown Boveri & Cie Verfahren zur herstellung von loetpads und bondpads auf duennschichthybridschaltungen
JPH01108798A (ja) * 1987-10-21 1989-04-26 Nec Corp プリント配線板の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100389314B1 (ko) * 2001-07-18 2003-06-25 엘지전자 주식회사 도금인입선 없는 인쇄회로기판의 제조방법

Also Published As

Publication number Publication date
EP0399768B1 (en) 1995-01-11
EP0399768A3 (en) 1991-07-17
DE69015879D1 (de) 1995-02-23
KR920007120B1 (ko) 1992-08-24
DE69015879T2 (de) 1995-05-04
US5042147A (en) 1991-08-27
EP0399768A2 (en) 1990-11-28
JPH02306690A (ja) 1990-12-20

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