KR890011037A - 전기적 접속접점과 그 형성방법 및 그것을 사용한 실장기판 - Google Patents
전기적 접속접점과 그 형성방법 및 그것을 사용한 실장기판 Download PDFInfo
- Publication number
- KR890011037A KR890011037A KR1019880016318A KR880016318A KR890011037A KR 890011037 A KR890011037 A KR 890011037A KR 1019880016318 A KR1019880016318 A KR 1019880016318A KR 880016318 A KR880016318 A KR 880016318A KR 890011037 A KR890011037 A KR 890011037A
- Authority
- KR
- South Korea
- Prior art keywords
- protrusion
- primary
- substrate
- electrode pad
- gold
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 전기적 접속접점의 측면도.
제2도는 본 발명의 제2실시예의 전기적 접속접점의 단면도.
제3도는 본 발명의 바람직한 실시예에 의한 실장기판의 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 기판 2 : 전극패드
3 : 캐필러리 4 : 구멍
5 : 금선 6 : 보올
7 : 1차 돌출부분 8 : 2차 돌출부분
9 : 금접점 10 : 칩서포트 프레임
11 : 전도성 터미널 12 : 전도성 접착제
13 : 열블럭 14 : 판
15 : 반도체 회로패턴
Claims (22)
- 기판위에 착설된 전극 패드위에서 형성된 전기적 접속접점에 있어서, 전극패드에 접착된 1차 돌출부분과 1차 돌출부분으로 형성되고 전극패드에 평행한 평면에서의 1차 돌출부분의 단면보다 더 작은 전극패드의 표면에 평행한 평면에서 단면을 가지고 있는 2차 돌출부분으로 구성되는 전기적 접속접점.
- 제1항에 있어서, 1차 돌출부분의 단면과 2차 돌출부분의 단면비율이 3/2 내지 5/1의 범위에 속하고 1차 돌출부분의 높이와 2차 돌출부분의 높이에 비율이 1/2 내지 2/1의 범위에 속하는 전기적 접속접점.
- 제1항에 있어서, 1차 돌출부분의 폭이 60 내지 120㎛의 범위에 속하는 전기적 접속접점.
- 제1항에 있어서, 1차 2차 돌출부분의 높이의 합이 30 내지 90㎛의 범위에 속하는 전기적 접속접점.
- 제1항에 있어서, 1차 2차 돌출부분이 금, 구리, 알루미늄 혹은 금, 구리, 알루미늄의 1종을 주성분으로 함유하는 합금으로 이루어진 전기적 접속접점.
- 기판의 전극패드위에서 형성된 전기적 접속접점에 있어서, 전극패드에 부착된 1차 돌출부분과 1차 돌출부분위에 형성되고 루우프형태로 굽혀진 전도성 와이어로 형성된 2차 돌출부분으로 구성되는 전기적 접속접점.
- 제6항에 있어서, 1차 2차 돌출부분은 금, 구리, 알루미늄 또는 하나의 주성분으로 금, 구리 알루미늄의 1종을 주성분으로 함유하는 합금으로 이루어진 전기적 접속접점.
- 다수의 전도성 터미널이 설치된 1차 기판과 1차 기판의 전도성 터미널이 일치하는 위치에서 각각 다수의 전극패드가 설치된 2차 기판과 다수의 전극패드위에 각각 형성되고 같은 전극패드에 부착된 1차 돌출부분 및 2차 돌출부분의 단면에 평행한 1차 돌출부분의 단면보다 전극패드에 평행한 평면에서의 2차 돌출부분의 단면이 더 적은 단면을 가지고 1차 돌출부분위에서 형성된 2차 돌출부분으로 구성되는 전기적 접속접점과 전기적 접속접점을 1차 기판의 해당 전도성 터미널에 각각 접착하는 전도성 접착제 방울들로 구성되는 실장기판.
- 제8항에 있어서, 상기 전도성 접착제의 각 방울은 실제적으로 2차 돌출부분이 형성되는 1차 돌출부분의 표면에만 접촉하는 실장기판.
- 제8항에 있어서, 상기 전도성 접착제가 유연한 실장기판.
- 제8항에 있어서, 상기 전극패드의 표면에 평행한 1차 돌출부분의 단면적대 1차 돌출부분의 단면에 평행한 2차 돌출부분의 단면적의 비율은 3/2 내지 5/1의 범위에 속하고 1차 돌출부분의 높이와 2차 돌출부분의 높이의 비율은 1/2 내지 2/1의 범위에 속하는 실장기판.
- 제8항에 있어서, 상기 1차 돌출부분의 폭은 60 내지 120㎛의 범위에 속하는 실장기판.
- 제8항에 있어서, 상기 1차 돌출부분과 2차 돌출부분의 높이에 합은 30 내지 90㎛의 범위에 속하는 실장기판.
- 제8항에 있어서, 상기 전기적 접속접점이 금, 구리, 알루미늄이나 또는 금, 구리, 알루미늄의 1종을 주성분으로 포함하는 합금으로 이루어진 실장기판.
- 다수의 전도성 터미널이 설치된 1차 기판과 1차 기판의 전도성 터미널에 부합하는 위치에 있는 다수의 전극패드가 설치된 2차 기판과 2차 기판의 전극패드위에서 각각 형성하고 전극패드에 부착된 1차 돌출부분과 1차 돌출부분위에 형성되고 루우프형태로 굽혀진 전도성 와이어로 형성된 2차 돌출부분으로 구성되는 다수의 전기적 접속접점과 전기적 접속접점을 1차 기판의 해당 전도성 터미널에 접착하는 전도성 접착제의 방울들로 구성되는 실장기판.
- 제15항에 있어서, 상기 전도성 접착제의 방울은 2차 돌출부분이 형성되는 1차 돌출부분의 표면에만 실제적으로 접촉하는 실장기판.
- 제15항에 있어서, 상기 전도성 접착제는 유연성이 있는 실장기판.
- 제15항에 있어서, 상기 전기적 접속접점은 금, 구리, 알루미늄 또 금, 구리, 알루미늄의 1종을 주성분으로 포함하는 합금으로 이루어진 실장기판.
- 1차 돌출부분과 루우프형태의 2차 돌출부분으로 구성되는 전기적 접속접점을 형성하는 방법에 있어서, 1차 돌출부분을 형성하기 위하여 캐필레리로 기판위에 형성된 전극패드에 전도성 와이어의 자유끝단에서 형성된 보올을 고착하기 위한 첫째단계와 캐필레리로 2차 돌출부분을 형성하기 위해 1차 돌출부분위에서 루우프형태로 전도성 와이어를 루우핑하고 루우프의 자유끝단에서 전도성와이어를 절단하는 둘째단계로 구성되는 전기적 접속접점을 형성하기 위한 방법.
- 제19항에 있어서, 상기 전도성 와이어는 금, 구리, 알루미늄 또는 금, 구리, 알루미늄의 1종을 주성분으로 함유하는 합금으로 이루어진 전기적 접속접점을 형성하기 위한 방법.
- 제19항에 있어서, 상기 2차 공정에서 전도성 와이어를 루우핑하여 형성된 전도성 와이어의 루우프 끝단이 1차 돌출부분에 고정되고 전도성 와이어가 루우프의 자유끝단에서 절단되는 전기적 접속접점을 형성하기 위한 방법.
- 제19항에 있어서, 상기 제2차 공정에서 전도성 와이어의 루우핑으로 형성된 전도성 와이어 루우프의 자유끝단이 1차 돌출부분이 형성된 전극패드의 1차 돌출부위에 고정된 후에 전도성 와이어가 루우프로부터 절단되는 전기적 접속접점을 형성하기 위한 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62309805A JP2506861B2 (ja) | 1987-12-08 | 1987-12-08 | 電気的接続接点の形成方法 |
JP62-309805 | 1987-12-08 | ||
JP18493688A JPH063820B2 (ja) | 1988-07-25 | 1988-07-25 | 半導体装置の実装方法 |
JP63-184936 | 1988-07-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890011037A true KR890011037A (ko) | 1989-08-12 |
KR910009780B1 KR910009780B1 (ko) | 1991-11-30 |
Family
ID=26502799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880016318A KR910009780B1 (ko) | 1987-12-08 | 1988-12-08 | 전기적 접속접점과 그 형성방법 및 그것을 사용한 실장기판 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5014111A (ko) |
EP (1) | EP0320244B1 (ko) |
KR (1) | KR910009780B1 (ko) |
DE (1) | DE3888476T2 (ko) |
HK (1) | HK89096A (ko) |
Families Citing this family (139)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917707A (en) | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US5476211A (en) | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
US5172851A (en) * | 1990-09-20 | 1992-12-22 | Matsushita Electronics Corporation | Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device |
US5296649A (en) * | 1991-03-26 | 1994-03-22 | The Furukawa Electric Co., Ltd. | Solder-coated printed circuit board and method of manufacturing the same |
KR940001149B1 (ko) * | 1991-04-16 | 1994-02-14 | 삼성전자 주식회사 | 반도체 장치의 칩 본딩 방법 |
JP3044872B2 (ja) * | 1991-09-25 | 2000-05-22 | ソニー株式会社 | 半導体装置 |
US5245750A (en) * | 1992-02-28 | 1993-09-21 | Hughes Aircraft Company | Method of connecting a spaced ic chip to a conductor and the article thereby obtained |
EP0560072A3 (en) * | 1992-03-13 | 1993-10-06 | Nitto Denko Corporation | Anisotropic electrically conductive adhesive film and connection structure using the same |
FR2696279B1 (fr) * | 1992-09-25 | 1994-11-18 | Thomson Csf | Procédé pour permettre le montage d'une puce sur un substrat et puce préparée selon le procédé. |
US5334804A (en) * | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US5545589A (en) * | 1993-01-28 | 1996-08-13 | Matsushita Electric Industrial Co., Ltd. | Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device |
US5249732A (en) * | 1993-02-09 | 1993-10-05 | National Semiconductor Corp. | Method of bonding semiconductor chips to a substrate |
US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
US5485949A (en) * | 1993-04-30 | 1996-01-23 | Matsushita Electric Industrial Co., Ltd. | Capillary for a wire bonding apparatus and a method for forming an electric connection bump using the capillary |
US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
JP3115155B2 (ja) * | 1993-05-28 | 2000-12-04 | 株式会社東芝 | 半導体装置およびその製造方法 |
US20070228110A1 (en) * | 1993-11-16 | 2007-10-04 | Formfactor, Inc. | Method Of Wirebonding That Utilizes A Gas Flow Within A Capillary From Which A Wire Is Played Out |
US20020053734A1 (en) * | 1993-11-16 | 2002-05-09 | Formfactor, Inc. | Probe card assembly and kit, and methods of making same |
US5820014A (en) | 1993-11-16 | 1998-10-13 | Form Factor, Inc. | Solder preforms |
US20030199179A1 (en) * | 1993-11-16 | 2003-10-23 | Formfactor, Inc. | Contact tip structure for microelectronic interconnection elements and method of making same |
US6835898B2 (en) * | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
US7073254B2 (en) * | 1993-11-16 | 2006-07-11 | Formfactor, Inc. | Method for mounting a plurality of spring contact elements |
US5650918A (en) * | 1993-11-25 | 1997-07-22 | Nec Corporation | Semiconductor device capable of preventing occurrence of a shearing stress |
US5466635A (en) * | 1994-06-02 | 1995-11-14 | Lsi Logic Corporation | Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
US5813115A (en) * | 1994-08-03 | 1998-09-29 | Matsushita Electric Industrial Co., Ltd. | Method of mounting a semiconductor chip on a wiring substrate |
EP1408337A3 (en) * | 1994-11-15 | 2007-09-19 | FormFactor, Inc. | Probe card assembly |
US5559054A (en) * | 1994-12-23 | 1996-09-24 | Motorola, Inc. | Method for ball bumping a semiconductor device |
US5686353A (en) * | 1994-12-26 | 1997-11-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US5665989A (en) * | 1995-01-03 | 1997-09-09 | Lsi Logic | Programmable microsystems in silicon |
US5537738A (en) * | 1995-02-10 | 1996-07-23 | Micron Display Technology Inc. | Methods of mechanical and electrical substrate connection |
JP3252153B2 (ja) * | 1995-03-10 | 2002-01-28 | エルク ザケル | 隆起接点メタライゼーションを形成する方法及びボンディングツール |
US20100065963A1 (en) | 1995-05-26 | 2010-03-18 | Formfactor, Inc. | Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out |
CN1107979C (zh) | 1995-07-14 | 2003-05-07 | 松下电器产业株式会社 | 半导体器件的电极结构、形成方法及安装体和半导体器件 |
DE19535775C2 (de) * | 1995-09-26 | 2000-06-21 | Siemens Ag | Verfahren zum elektrischen Verbinden eines Kontaktfeldes eines Halbleiterchips mit zumindest einer Kontaktfläche sowie danach hergestellte Chipkarte |
US5874354A (en) * | 1995-09-26 | 1999-02-23 | Siemens Aktiengesellschaft | Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method |
US5650667A (en) * | 1995-10-30 | 1997-07-22 | National Semiconductor Corporation | Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created |
US5668058A (en) * | 1995-12-28 | 1997-09-16 | Nec Corporation | Method of producing a flip chip |
US6001724A (en) * | 1996-01-29 | 1999-12-14 | Micron Technology, Inc. | Method for forming bumps on a semiconductor die using applied voltage pulses to an aluminum wire |
US5994152A (en) | 1996-02-21 | 1999-11-30 | Formfactor, Inc. | Fabricating interconnects and tips using sacrificial substrates |
US8033838B2 (en) | 1996-02-21 | 2011-10-11 | Formfactor, Inc. | Microelectronic contact structure |
JP2951882B2 (ja) * | 1996-03-06 | 1999-09-20 | 松下電器産業株式会社 | 半導体装置の製造方法及びこれを用いて製造した半導体装置 |
JP3146345B2 (ja) * | 1996-03-11 | 2001-03-12 | アムコー テクノロジー コリア インコーポレーティド | バンプチップスケール半導体パッケージのバンプ形成方法 |
JPH09252005A (ja) * | 1996-03-15 | 1997-09-22 | Shinkawa Ltd | バンプ形成方法 |
JP3349886B2 (ja) | 1996-04-18 | 2002-11-25 | 松下電器産業株式会社 | 半導体素子の2段突起形状バンプの形成方法 |
US6022761A (en) * | 1996-05-28 | 2000-02-08 | Motorola, Inc. | Method for coupling substrates and structure |
JP2842378B2 (ja) * | 1996-05-31 | 1999-01-06 | 日本電気株式会社 | 電子回路基板の高密度実装構造 |
JP3610999B2 (ja) * | 1996-06-07 | 2005-01-19 | 松下電器産業株式会社 | 半導体素子の実装方法 |
JP3558449B2 (ja) * | 1996-06-10 | 2004-08-25 | 松下電器産業株式会社 | 電子部品構体 |
EP1158578B1 (en) * | 1996-10-01 | 2004-06-30 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit or circuit board with bump electrode and manufacturing method thereof |
JP2848357B2 (ja) * | 1996-10-02 | 1999-01-20 | 日本電気株式会社 | 半導体装置の実装方法およびその実装構造 |
JP3344235B2 (ja) * | 1996-10-07 | 2002-11-11 | 株式会社デンソー | ワイヤボンディング方法 |
DE69628018D1 (de) * | 1996-10-30 | 2003-06-12 | St Microelectronics Sa | Halbleiterpackung mit mechanisch und elektrisch verbundenen Trägerelementen |
US6133072A (en) | 1996-12-13 | 2000-10-17 | Tessera, Inc. | Microelectronic connector with planar elastomer sockets |
US5898215A (en) | 1996-12-16 | 1999-04-27 | Motorola, Inc. | Microelectronic assembly with connection to a buried electrical element, and method for forming same |
JP3150347B2 (ja) * | 1996-12-27 | 2001-03-26 | 松下電器産業株式会社 | 回路基板への電子部品の実装方法及びその装置 |
JPH10233413A (ja) * | 1997-02-21 | 1998-09-02 | Nec Kansai Ltd | 半導体装置およびその製造方法並びに配線基板 |
US5856912A (en) * | 1997-03-04 | 1999-01-05 | Motorola Inc. | Microelectronic assembly for connection to an embedded electrical element, and method for forming same |
US6165888A (en) * | 1997-10-02 | 2000-12-26 | Motorola, Inc. | Two step wire bond process |
US6001723A (en) * | 1997-12-24 | 1999-12-14 | National Semiconductor Corporation | Application of wire bond loop as integrated circuit package component interconnect |
US5969461A (en) * | 1998-04-08 | 1999-10-19 | Cts Corporation | Surface acoustic wave device package and method |
JP2000133672A (ja) * | 1998-10-28 | 2000-05-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6177729B1 (en) * | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6227437B1 (en) | 1999-08-24 | 2001-05-08 | Kulicke & Soffa Industries Inc. | Solder ball delivery and reflow apparatus and method of using the same |
US6386433B1 (en) | 1999-08-24 | 2002-05-14 | Kulicke & Soffa Investments, Inc. | Solder ball delivery and reflow apparatus and method |
US6469394B1 (en) | 2000-01-31 | 2002-10-22 | Fujitsu Limited | Conductive interconnect structures and methods for forming conductive interconnect structures |
JP4000743B2 (ja) | 2000-03-13 | 2007-10-31 | 株式会社デンソー | 電子部品の実装方法 |
US6321976B1 (en) * | 2000-05-22 | 2001-11-27 | Siliconware Precision Industries Co., Ltd. | Method of wire bonding for small clearance |
JP4456234B2 (ja) * | 2000-07-04 | 2010-04-28 | パナソニック株式会社 | バンプ形成方法 |
DE10038330C2 (de) * | 2000-08-05 | 2002-07-11 | Bosch Gmbh Robert | Lötverfahren zur Befestigung elektrischer Bauelemente |
US6511865B1 (en) | 2000-09-20 | 2003-01-28 | Charles W. C. Lin | Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly |
US6350632B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with ball bond connection joint |
US6350386B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
US6448108B1 (en) | 2000-10-02 | 2002-09-10 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6544813B1 (en) | 2000-10-02 | 2003-04-08 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US7414319B2 (en) * | 2000-10-13 | 2008-08-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with metal containment wall and solder terminal |
US6576539B1 (en) | 2000-10-13 | 2003-06-10 | Charles W.C. Lin | Semiconductor chip assembly with interlocked conductive trace |
US6984576B1 (en) | 2000-10-13 | 2006-01-10 | Bridge Semiconductor Corporation | Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip |
US6537851B1 (en) | 2000-10-13 | 2003-03-25 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace to a semiconductor chip |
US6492252B1 (en) | 2000-10-13 | 2002-12-10 | Bridge Semiconductor Corporation | Method of connecting a bumped conductive trace to a semiconductor chip |
US6699780B1 (en) | 2000-10-13 | 2004-03-02 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching |
US6548393B1 (en) | 2000-10-13 | 2003-04-15 | Charles W. C. Lin | Semiconductor chip assembly with hardened connection joint |
US7129113B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture |
US7190080B1 (en) | 2000-10-13 | 2007-03-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
US7262082B1 (en) | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
US6949408B1 (en) | 2000-10-13 | 2005-09-27 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
US6908788B1 (en) | 2000-10-13 | 2005-06-21 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using a metal base |
US7094676B1 (en) | 2000-10-13 | 2006-08-22 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US6440835B1 (en) | 2000-10-13 | 2002-08-27 | Charles W. C. Lin | Method of connecting a conductive trace to a semiconductor chip |
US7132741B1 (en) | 2000-10-13 | 2006-11-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with carved bumped terminal |
US6667229B1 (en) | 2000-10-13 | 2003-12-23 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip |
US6673710B1 (en) | 2000-10-13 | 2004-01-06 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip |
US7071089B1 (en) | 2000-10-13 | 2006-07-04 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a carved bumped terminal |
US7319265B1 (en) | 2000-10-13 | 2008-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with precision-formed metal pillar |
US7075186B1 (en) | 2000-10-13 | 2006-07-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with interlocked contact terminal |
US6876072B1 (en) | 2000-10-13 | 2005-04-05 | Bridge Semiconductor Corporation | Semiconductor chip assembly with chip in substrate cavity |
US7264991B1 (en) | 2000-10-13 | 2007-09-04 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using conductive adhesive |
US6872591B1 (en) | 2000-10-13 | 2005-03-29 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a conductive trace and a substrate |
US6576493B1 (en) | 2000-10-13 | 2003-06-10 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
US7129575B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped metal pillar |
US6444489B1 (en) | 2000-12-15 | 2002-09-03 | Charles W. C. Lin | Semiconductor chip assembly with bumped molded substrate |
US6653170B1 (en) | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
JP3943416B2 (ja) * | 2002-03-07 | 2007-07-11 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7229906B2 (en) * | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
US6815836B2 (en) * | 2003-03-24 | 2004-11-09 | Texas Instruments Incorporated | Wire bonding for thin semiconductor package |
JP4104490B2 (ja) * | 2003-05-21 | 2008-06-18 | オリンパス株式会社 | 半導体装置の製造方法 |
US7314781B2 (en) * | 2003-11-05 | 2008-01-01 | Lsi Corporation | Device packages having stable wirebonds |
US7993983B1 (en) | 2003-11-17 | 2011-08-09 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with chip and encapsulant grinding |
US7425759B1 (en) | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
US7538415B1 (en) | 2003-11-20 | 2009-05-26 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal, filler and insulative base |
US7446419B1 (en) | 2004-11-10 | 2008-11-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar of stacked metal balls |
US7268421B1 (en) | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
DE102004059389B4 (de) * | 2004-12-09 | 2012-02-23 | Infineon Technologies Ag | Halbleiterbauelement mit Ausgleichsmetallisierung |
US7851348B2 (en) * | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US7786592B2 (en) * | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US8456015B2 (en) * | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7989958B2 (en) * | 2005-06-14 | 2011-08-02 | Cufer Assett Ltd. L.L.C. | Patterned contact |
US7687400B2 (en) * | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7560813B2 (en) | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
US7767493B2 (en) * | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US20060281303A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Tack & fuse chip bonding |
US20070222087A1 (en) * | 2006-03-27 | 2007-09-27 | Sangdo Lee | Semiconductor device with solderable loop contacts |
US7687397B2 (en) * | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
US20070281460A1 (en) * | 2006-06-06 | 2007-12-06 | Cubic Wafer, Inc. | Front-end processed wafer having through-chip connections |
US20100186991A1 (en) * | 2006-10-18 | 2010-07-29 | Kulicke And Soffa Industries, Inc. | conductive bumps, wire loops including the improved conductive bumps, and methods of forming the same |
US7811863B1 (en) | 2006-10-26 | 2010-10-12 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment |
US7494843B1 (en) | 2006-12-26 | 2009-02-24 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding |
US7670874B2 (en) | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
US8193624B1 (en) | 2008-02-25 | 2012-06-05 | Amkor Technology, Inc. | Semiconductor device having improved contact interface reliability and method therefor |
TW201123377A (en) * | 2009-12-16 | 2011-07-01 | Raydium Semiconductor Corp | Electronic chip and substrate with void |
US9087815B2 (en) * | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) * | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
TWI736859B (zh) * | 2019-03-18 | 2021-08-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1170555B (de) * | 1956-07-23 | 1964-05-21 | Siemens Ag | Verfahren zum Herstellen eines Halbleiter-bauelements mit drei Zonen abwechselnd entgegengesetzten Leitungstyps |
US3357090A (en) * | 1963-05-23 | 1967-12-12 | Transitron Electronic Corp | Vibratory welding tip and method of welding |
US3373481A (en) * | 1965-06-22 | 1968-03-19 | Sperry Rand Corp | Method of electrically interconnecting conductors |
JPS4952973A (ko) * | 1972-09-22 | 1974-05-23 | ||
JPS571896B2 (ko) * | 1973-04-06 | 1982-01-13 | ||
US3878008A (en) * | 1974-02-25 | 1975-04-15 | Us Navy | Method of forming high reliability mesa diode |
US4067104A (en) * | 1977-02-24 | 1978-01-10 | Rockwell International Corporation | Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components |
US4427715A (en) * | 1978-07-03 | 1984-01-24 | National Semiconductor Corporation | Method of forming expanded pad structure |
JPS5552242A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Semiconductor device |
JPS5917974B2 (ja) * | 1978-12-19 | 1984-04-24 | 三菱電機株式会社 | ワイヤボンデイング装置 |
JPS574130A (en) * | 1980-06-10 | 1982-01-09 | Sanyo Electric Co Ltd | Adhesion of semiconductor element |
JPS5741807A (en) * | 1980-08-25 | 1982-03-09 | Magnitogorsk Metallurg | Multi-roll pass stand |
NL184184C (nl) * | 1981-03-20 | 1989-05-01 | Philips Nv | Werkwijze voor het aanbrengen van kontaktverhogingen op kontaktplaatsen van een electronische microketen. |
JPS58215057A (ja) * | 1982-06-09 | 1983-12-14 | Hitachi Ltd | バンプ形成装置 |
JPS595637A (ja) * | 1982-07-02 | 1984-01-12 | Hitachi Ltd | 半導体素子の実装構造および実装方法 |
JPS5988861A (ja) * | 1982-11-12 | 1984-05-22 | Matsushita Electric Ind Co Ltd | 金属リ−ドと電極との接合方法 |
JPS61287136A (ja) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US4661192A (en) * | 1985-08-22 | 1987-04-28 | Motorola, Inc. | Low cost integrated circuit bonding process |
US4717066A (en) * | 1986-02-24 | 1988-01-05 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of bonding conductors to semiconductor devices |
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
US4750666A (en) * | 1986-04-17 | 1988-06-14 | General Electric Company | Method of fabricating gold bumps on IC's and power chips |
JPS63150931A (ja) * | 1986-12-15 | 1988-06-23 | Nec Corp | 半導体装置 |
US4955523A (en) * | 1986-12-17 | 1990-09-11 | Raychem Corporation | Interconnection of electronic components |
DE3703694A1 (de) * | 1987-02-06 | 1988-08-18 | Dynapert Delvotec Gmbh | Ball-bondverfahren und vorrichtung zur durchfuehrung derselben |
JPS63220549A (ja) * | 1987-03-09 | 1988-09-13 | Nec Corp | 集積回路装置 |
-
1988
- 1988-12-02 US US07/279,101 patent/US5014111A/en not_active Expired - Lifetime
- 1988-12-07 DE DE3888476T patent/DE3888476T2/de not_active Expired - Lifetime
- 1988-12-07 EP EP88311598A patent/EP0320244B1/en not_active Expired - Lifetime
- 1988-12-08 KR KR1019880016318A patent/KR910009780B1/ko not_active IP Right Cessation
-
1990
- 1990-10-30 US US07/605,096 patent/US5090119A/en not_active Expired - Lifetime
-
1996
- 1996-05-23 HK HK89096A patent/HK89096A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5014111A (en) | 1991-05-07 |
EP0320244A2 (en) | 1989-06-14 |
DE3888476T2 (de) | 1994-09-29 |
EP0320244A3 (en) | 1990-10-10 |
US5090119A (en) | 1992-02-25 |
HK89096A (en) | 1996-05-31 |
KR910009780B1 (ko) | 1991-11-30 |
EP0320244B1 (en) | 1994-03-16 |
DE3888476D1 (de) | 1994-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR890011037A (ko) | 전기적 접속접점과 그 형성방법 및 그것을 사용한 실장기판 | |
US5367435A (en) | Electronic package structure and method of making same | |
KR940022755A (ko) | 반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame) | |
KR830004676A (ko) | 회로 패키지들의 제조방법 | |
KR960012397A (ko) | 칩 사이즈 패키지형 반도체 장치의 제조 방법 | |
KR920001701A (ko) | 반도체 장치 및 그 제조방법 | |
KR890016585A (ko) | 세라믹-금속 복합물 기판, 그것으로 구성된 회로 기판 및 그 제조방법 | |
KR930009047A (ko) | 개량된 리드를 갖는 반도체장치 | |
KR980012316A (ko) | 반도체 장치 및 그 제조 방법 | |
JP3907145B2 (ja) | チップ電子部品 | |
US5531860A (en) | Structure and method for providing a lead frame with enhanced solder wetting leads | |
US20070096271A1 (en) | Substrate frame | |
KR900019545A (ko) | 표면장착용 배선기판의 제조방법 | |
EP0513743A2 (en) | Semiconductor package for surface mounting | |
US5406119A (en) | Lead frame | |
JPS63275127A (ja) | 半導体チップの実装体 | |
KR100208635B1 (ko) | 표면 실장형 반도체 장치 | |
KR960035997A (ko) | 반도체 패키지 및 그 제조방법 | |
US20050205988A1 (en) | Die package with higher useable die contact pad area | |
JPH0661609A (ja) | 回路基板 | |
JP3894336B2 (ja) | 電子部品 | |
JPH113955A (ja) | 半導体チップ搭載ボード | |
JPH06112395A (ja) | 混成集積回路装置 | |
CN111816636B (zh) | 封装载板以及封装结构 | |
JP2830221B2 (ja) | ハイブリッド集積回路のマウント構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20081126 Year of fee payment: 18 |
|
EXPY | Expiration of term |