KR940008061A - 기판상의 칩 어셈블리 및 이의 제조 방법 - Google Patents
기판상의 칩 어셈블리 및 이의 제조 방법 Download PDFInfo
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- KR940008061A KR940008061A KR1019930020080A KR930020080A KR940008061A KR 940008061 A KR940008061 A KR 940008061A KR 1019930020080 A KR1019930020080 A KR 1019930020080A KR 930020080 A KR930020080 A KR 930020080A KR 940008061 A KR940008061 A KR 940008061A
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Abstract
중앙 접촉부(35)를 갖는 반도체 칩(32)가 회로 기판(31)내의 연장된 개구(33)내에 중심이 맞춰진 중앙 접촉부(35)에 회로 기판(31) 하부에 활성 측면을 장착한 기판상의 칩 어셈블리 및 이의 제조 방법이 기술되었다. 중앙 접촉부(35)는 반도체 칩(32)가 장착된 회로 기판(31)의 대향 측면상에 회로 기판(31)상의 접촉부(34)에 회로 기판(31)내의 개구 (33)을 통해 접속된다. 반도체 칩(32)는 반도체 칩의 고 배치 밀도를 제공하기 위한 회로 기판(31)의 대향 측면상에 교대로 장착된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 기판상의 칩 어셈블리를 도시한 도면.
제4도는 본 발명의 기판상의 칩 어셈블리의 측면도.
제5도는 본 발명의 기판상의 칩 어셈블리 평면도.
Claims (12)
1개 이상의 활성 표면을 갖는 반도체 칩 및 2개의 장착 표면을 갖는 회로 기판을 포함하는 기판상의 반도체 칩 어셈블리에 있어서, 회로기판의 길이에 대해 횡으로 연장하는 다수의 개구를 갖는 회로 기판, 상기 회로 기판의 각각 2개의 장착 표면상의 다수의 회로 접촉부, 회로 기판의 표면에 부착된 활성 표면이 상기 회로 기판의 대향 측면상에 교대로 장착되고, 회로 기판내의 다수의 개구들중 한 개구위에 중심이 맞춰진 각각의 반도체 칩 및 활성 면상의 접합 패드의 중앙 어레이를 갖는 다수의 반도체 칩 및 회로 기판내의 개구를 통해 연장하는 각각의 반도체 칩상의 접합 패드의 중앙 어레이에 접속되고 반도체 칩이 부착된 회로 기판에 대향하는 회로 기판의 측면상에 회로 접촉부가 접합된 접합 배선을 포함하는 것을 특징으로 하는 반도체 칩 어셈블리.
제1항에 있어서, 접합 배선이 반도체 칩상의 접합 패드에서 볼 결합되는 것을 특징으로 하는 반도체 칩 어셈블리.
제1항에 있어서, 접합 배선이 반도체 칩상의 접합 패드에 웨지 결합되는 것을 특징으로 하는 반도체 칩 어셈블리.
제1항에 있어서, 회로 기판의 각 측면상에 교대로 장착된 반도체 칩의 2이상의 행을 포함하는 것을 특징으로 하는 반도체 칩 어셈블리.
제1항에 있어서, 각각의 반도체 칩이 접착제로 회로 기판에 와이어 본딩 이전에 부착된 활성 면을 갖는 것을 특징으로 하는 반도체 칩 어셈블리.
1개 이상의 활성 표면을 갖는 반도체 칩 및 2개의 장착 표면을 갖는 회로 기판을 포함하는 기판상의 반도체 칩 어셈블리에 있어서, 회로기판의 길이에 대해 횡으로 연장하는 다수의 개구를 갖는 회로 기판, 상기 회로 기판의 각각 2개의 장착 표면상의 다수의 회로 접촉부, 회로 기판의 표면에 접착제로 부착된 활성 표면이 상기 회로 기판의 대향 측면상에 교대로 장착되고, 회로 기판내의 다수의 개구중 한 개구위에 중심이 맞춰진 각각의 반도체 칩 및 활성면상의 접합 패드의 중앙 어레이를 갖는 다수의 반도체 칩, 및 회로 기판내의 개구를 통해 연장하는 반도체 칩상의 접합 패드의 중앙, 어레이에 접속되고 반도체 칩이 부착되는 회로 기판에 대향하는 회로 기판의 측면상의 회로 접촉부에 접합되는 접합 배선을 포함하는 것을 특징으로 하는 반도체 칩 어셈블리.
제6항에 있어서, 접합 배선이 반도체 칩상의 접합 패드상에 웨지 결합되는 것을 특징으로 하는 반도체 칩 어셈블리.
제6항에 있어서, 회로 기판의 각 측면상에 교대로 장착된 반도체 칩의 2 이상의 행을 포함하는 것을 특징으로 하는 반도체 칩 어셈블리.
제6항에 있어서, 각각의 반도체 칩은 접착제로 회로 기판에 와이어 본딩 이전에 부착된 활성 면을 갖는 것을 특징으로 하는 반도체 칩 어셈블리.
기판상의 칩 어셈블리를 제조하기 위한 방법에 있어서, 도전성 회로 및 접촉부를 각각 갖는 제1 및 제2 측면을 가지는 회로 기판을 준비하는 단계, 상기 회로 기판을 완전히 관통하여 연장하는 다수의 연장된 홀들을 형성하는 단계, 다수의 반도체 칩들중 한 칩의 중앙 접촉부가 상기 연장된 홀들중 하나에 중심이 맞워지도록 상기 회로 기판의 상기 제1 및 제2측면상의 한면에 중앙 접촉부를 갖는 다수의 반도체 칩을 장착하는 단계, 및 중앙 접촉부에 접촉되고, 연장된 홀을 관통하여 연장하며, 반도체 칩이 장착되는 측면과 대향하여 회로 기판의 한 측면상의 회로 기판에 접속되는 접속 배선으로 상기 반도체 칩 상의 각각의 상기 중앙 접촉부를 상기 회로 기판상의 접촉부에 접속하는 단계를 포함하는 것을 특징으로 하는 방법.
제10항에 있어서, 반도체 칩을 회로 기판에 접착제로 부착하는 단계를 포함하는 것을 특징으로 하는 방법.
제10항에 있어서, 상기 회로 기판을 관통하여 연장하는 상기 다수의 연장된 홀이 서로 나란한 것을 특징으로 하는 방법.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/953,634 US5243497A (en) | 1992-09-29 | 1992-09-29 | Chip on board assembly |
US07/953,634 | 1992-09-29 |
Publications (1)
Publication Number | Publication Date |
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KR940008061A true KR940008061A (ko) | 1994-04-28 |
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ID=25494297
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Application Number | Title | Priority Date | Filing Date |
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KR1019930020080A KR940008061A (ko) | 1992-09-29 | 1993-09-28 | 기판상의 칩 어셈블리 및 이의 제조 방법 |
Country Status (6)
Country | Link |
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US (1) | US5243497A (ko) |
EP (1) | EP0590915B1 (ko) |
JP (1) | JP3397852B2 (ko) |
KR (1) | KR940008061A (ko) |
DE (1) | DE69313062T2 (ko) |
TW (1) | TW243551B (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100305570B1 (ko) * | 1998-07-01 | 2001-10-19 | 이형도 | 인쇄회로기판및그제조방법 |
KR20200066199A (ko) * | 2018-11-30 | 2020-06-09 | 주식회사 포스코 | 법랑용 강판 및 그 제조방법 |
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KR0177395B1 (ko) * | 1995-04-27 | 1999-05-15 | 문정환 | 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법 |
US5818698A (en) * | 1995-10-12 | 1998-10-06 | Micron Technology, Inc. | Method and apparatus for a chip-on-board semiconductor module |
SG79950A1 (en) * | 1997-10-22 | 2001-04-17 | Texas Instr Singapore Pte Ltd | Double sided single inline memory module |
US6456502B1 (en) * | 1998-09-21 | 2002-09-24 | Compaq Computer Corporation | Integrated circuit device/circuit board connection apparatus |
TW368707B (en) * | 1998-10-27 | 1999-09-01 | Tech Field Co Ltd | Packaging method for semiconductor die and the product of the same |
US6815251B1 (en) | 1999-02-01 | 2004-11-09 | Micron Technology, Inc. | High density modularity for IC's |
US6683377B1 (en) * | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
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US7687920B2 (en) * | 2008-04-11 | 2010-03-30 | Stats Chippac Ltd. | Integrated circuit package-on-package system with central bond wires |
WO2012071325A1 (en) * | 2010-11-24 | 2012-05-31 | Tessera, Inc. | Lead structures with vertical offsets |
JP2017122625A (ja) * | 2016-01-06 | 2017-07-13 | 株式会社豊田中央研究所 | データ収録装置 |
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JPS5893263A (ja) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | 密閉方法 |
US4807019A (en) * | 1987-04-24 | 1989-02-21 | Unisys Corporation | Cavity-up-cavity-down multichip integrated circuit package |
US4891789A (en) * | 1988-03-03 | 1990-01-02 | Bull Hn Information Systems, Inc. | Surface mounted multilayer memory printed circuit board |
EP0339154B1 (en) * | 1988-04-26 | 1994-11-17 | Citizen Watch Co. Ltd. | Memory card |
US5185502A (en) * | 1989-12-01 | 1993-02-09 | Cray Research, Inc. | High power, high density interconnect apparatus for integrated circuits |
US5099309A (en) * | 1990-04-30 | 1992-03-24 | International Business Machines Corporation | Three-dimensional memory card structure with internal direct chip attachment |
-
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- 1992-09-29 US US07/953,634 patent/US5243497A/en not_active Expired - Lifetime
-
1993
- 1993-09-27 DE DE69313062T patent/DE69313062T2/de not_active Expired - Fee Related
- 1993-09-27 EP EP93307645A patent/EP0590915B1/en not_active Expired - Lifetime
- 1993-09-28 KR KR1019930020080A patent/KR940008061A/ko not_active Application Discontinuation
- 1993-09-28 JP JP24181393A patent/JP3397852B2/ja not_active Expired - Fee Related
-
1994
- 1994-03-08 TW TW083101967A patent/TW243551B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100305570B1 (ko) * | 1998-07-01 | 2001-10-19 | 이형도 | 인쇄회로기판및그제조방법 |
KR20200066199A (ko) * | 2018-11-30 | 2020-06-09 | 주식회사 포스코 | 법랑용 강판 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
JPH06216182A (ja) | 1994-08-05 |
DE69313062T2 (de) | 1997-12-11 |
TW243551B (ko) | 1995-03-21 |
EP0590915A1 (en) | 1994-04-06 |
JP3397852B2 (ja) | 2003-04-21 |
DE69313062D1 (de) | 1997-09-18 |
EP0590915B1 (en) | 1997-08-13 |
US5243497A (en) | 1993-09-07 |
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