TW243551B - - Google Patents

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TW243551B
TW243551B TW083101967A TW83101967A TW243551B TW 243551 B TW243551 B TW 243551B TW 083101967 A TW083101967 A TW 083101967A TW 83101967 A TW83101967 A TW 83101967A TW 243551 B TW243551 B TW 243551B
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circuit board
semiconductor
wafer
bonding
semiconductor wafer
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TW083101967A
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

^43〇5χ
經濟部中央樣準局員工消費合作社印製 五、發明説明（ 本發明是關於半導體裝置，特別是晶片電路板總成及 製程，其中裸半導晶片交替裝在電路板的反侧。 發明背景 含晶片電路板總成中，半導體晶片通常裝在電路板一 侧。金線用來將半導體裝置上的接合墊片接到電路板上的 接點區。電路板上需要大面積，不僅要安裝半導體晶片， 還要提供互連的電路接點區以接到半導體裝置。 發明概述 本發明是含晶片電路板總成，其中裸半導體晶片交替 裝在電路板的反侧。每個半導體裝置使用中心接合墊片設 計。裸晶片裝在作用面下，而中心接合墊片在電路板開口 内的中心。中心接合墊片被球形或楔形接合到安裝裸晶片 之電路板反侧的電路板接點。半導體晶片的交替安裝^中 心接合墊片提供較高的電路板面積利用。 當配合附圖和申請專利範圍所提出的新穎特性時，從 本發明較佳實施例的以下説明會凸顯本發明所呈現的技術 進展及目標。 ； 圖式簡述 圖1是具有中心接合墊片的習知半導體； 圖2是標準的習知含晶片電路板總成； 圖3顯示依據本發明的含晶片電路板總成； —3 — .......................................-............................................裝.........................訂.....................線 (請先閲讀背面之注意事項再填寫本頁) —本紙張尺度適用中國國家標準（CNS)甲4规格（210x297公釐） ^43551
五、發明說明（ 經濟部t央標準局貝工消费合作社印製 圖本發明之含晶片電路板總k的侧視圖； 圖5是本發明之含晶片電路板總成的之視圖； 較佳實施例的描述 圖1是具_有中心接合墊片n的標準半導體晶片10〇 备圖2顯示使用含晶片電路板製程的標準電路板總成。 當半導體裝置21的接合墊片Μ沿著晶片周邊時，因需要安 裝晶片並建立晶片上的接合塾片23與電路板上的接點24之 間的連接，故晶片幻之電路板2〇的面積通常大於晶片。利 用較長的線長度丨2 ’具有中心接合墊片U的晶片1〇也能以 類似方式組合。晶片和21分別在28和29塗以齊封材料， 來贫封及保護裝置，並保持接合線定位。 圖3是本發明的等角投影圖。只顯示五個晶片。電路 板31具有交替裝在電路板S1之反侧的半導體晶片32 ^每個 半導體晶片21具有中心接合墊片35。每一晶片位於電路板31 的開口 33上方，使得接合墊片35在開口 33中心。每—接合 塾片35接到電路板的接點％。接點34是電路板S1上之電 路的一部分。管道置於一些接點中以接到其它層的電路板 。由於接合墊片35靠近接點34 ’故只需短的接合線將半導 體晶片接到電路板上的電路，更多的半導體晶片可置於每 一電路板上。 ' 圖4是含晶片電路板總成的侧視圖。裸半導體晶片32 由向溫黏著劑3la交替黏在電路板的反侧。板M覆上電 隔離的焊罩。每一晶片具有中心接合墊片配置。—陣列的 ........................................................................................................裝......................訂..................線 (請先《讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS>甲4规格（210x297公釐） ^43〇5l A6 B6 五、發明説明（ ） 接合墊片35遠離晶片邊緣。此陣列的墊片在電路板31的開 口 33上方中心。半導體32上的每一接合墊片以接合線32&球 形或楔形接合到黏著半導體晶片之電路板31反侧的各接點34( 未圖示）。藉著將半導體晶片交替裝在電路板反侧，並使 用中心接合墊片陣列，晶片可更靠近地裝在一起，提供較 高的裝置密度。在測試後，塗上保護塗層36。 圖5是含晶片電路板總成(3〇)的頂視圖。半導體晶片32 靠近裝在一起，而電路板的開口 33在每對半導體晶片之間 。如圖4所示，電路板31底侧的半導體晶片32具有在開口 33 上方中心之中心陣列的接合勢片，接合塾片35接到電路板31 之頂侧的接點區3 4。接合線3如從接合墊片延伸經過開口 3 3 ’接到電路板31反侧的接點34。顯示電路板Μ上的一列接 點在每對半導體晶片之間’但可用二列接點，視所需的電 路組態而定。 半導體接合塾片經由電路板接合到電路板反侧的接點 ’使得將半導體晶片接到電路板的最短接合線變得可能。 短的接合線不會延伸在半導體晶片上方（測試時對接合線 提供保護）’並對整個電路板總成提供低輸廓和高晶片設 置密度。 ” 只顯示一列半導體晶片交替裝在電路板上，但對特別 電路組態可安裝二列以上。 ------:::-...................................................................-裝----------------------訂.....................線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橒準局貝工消费合作社印製 ——5 一 -本紙張尺度適时s a家標準（GNS)甲4规格（210X297公着) ~ ------

Claims (1)

  1. 43351 A7 B7 C7 D7 六、申請專利範圍 1. 一種含晶片電路板半導體總成，包含具有至少一作用面 的半導體晶片和具有二個安裝表面的電路板，包括： 電路板，具有橫亙於電路板長度而延伸的多個開口； 多個電路接點，在該電路板二個安裝表面的每一面上；、 多個半導體晶片，交替裝在該電路板的反侧，而作用面 黏在電路板表面’每個半導體晶片具有在作用面上的中 心陣列接合墊片，每個半導體晶片上的中心陣列接合墊 片在電路板之多個開口其中一個的上方中心； 接合線，接到每個半導體晶片上的中心陣列接合墊片， 延伸通過電路板的開口，且接合到黏著半導體晶片之電 路板反侧的電路接點。 2. 如申請專利範圍第1項的半導體總成，其中接合線球形 接合到半導體晶片上的接合墊片。 3. 如申請專利範圍第1項的半導體總成，其中接合線楔形 接合到半導體晶片上的接合替片。 4. 如申請專利範圍第1項的半導體總成，包含至少二列交 替裝在電路板每一侧的半導體晶片。 5·如申請專利範圍第1項的半導體總成，其中每個半導體 晶片的作用面在線接合前以黏考劑黏在電路板Z 6.，含曰日片電路板半導體總成，包含具有至少一作用面 的半導體晶片和具有二個安裝表面的電路板，包括： 電路板，具有橫亙於電路板長度而延伸的多個開口； 多個，路接點，在該電路板二個安裝表面的每一面上； 多個半導禮晶片，交替裝在該電路板的反侧 ’而作用面, —6 — -----------------------裝------tr------線 (請先Μ讀背面之注意事項再塡寫本頁) «濟部中央樣準局霣工消费合作钍印製
    243551 A7 B7 C7 D7 經濟部中央標準局具工消費合作社印32 六、申請專利範園 以黏著劑黏在電路板表面，每個半導體晶片具有在作用 面上的中心陣列接合墊片，每個半導體晶片上的中心陣 列接合墊片在電路板之多個開口其中一個的上方中心； 接合線，接到每個半導體晶片上的中心陣列接合墊片， 延伸通過電路板的開口，且接合到黏著半導體晶片之電 路板反側的電路接點。 7. 如申請專利範圍第6項的半導體總成，其中接合線楔形 接合到半導體晶片上的接合塾片。 8. 如申請專利範圍第6項的半導體總成，包含至少二列交 替裝在電路板每一侧的半導體晶片。 9. 如申請專利範圍第6項的半導體總成，其中每個半導體 晶片的作用面在線接合前以黏著劑黏在電路板。 10. —種製造含晶片電路板綠成的方法，包括下列步驟·· 製備具有第一和第二侧的電路板，每一侧具有導電電路 和接點； 形成完全延伸通過該電路板的多個長形孔； 將具有中心接點的多個半導體晶片裝在該電路板第一和 第二侧的一面上，使得該多個半導體晶片其中一個的中 心接點在其中一個該長形孔中心； 將該半導體晶片上的每一中心接點以接合線接到該電路 板上的接點，接合線黏在中心接點，延伸通過長形孔， 接到在安裝半導體晶片之電路板反侧的電路板接點。 11. 如申請專利範圍第10項的方法，包含將半導體晶片以黏 著劑黏在電路板的步騾。 一 7 - (請先閲讀背面之注意事項再塡寫本頁) 丨裝， 訂_ 線- 本紙張尺度適用中國國家標準（CNS>甲4坑格（210 X 297公釐） ^43551 A7 B7 C7 D7 六、申請專利範圍12.如申請專利範圍第10項的方法，其中延伸通過該電路板 的多個長形孔互相平行。 (請先閲讀背面之注意事項再塡寫本頁) T 經濟部中央標準局员工消费合作社印製 本紙張尺度適用中S國家標準（CMS)甲4規格（210 X 297公釐）
TW083101967A 1992-09-29 1994-03-08 TW243551B (zh)

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