KR870011692A - 반도체 장치 패키지 - Google Patents

반도체 장치 패키지 Download PDF

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KR870011692A
KR870011692A KR870005153A KR870005153A KR870011692A KR 870011692 A KR870011692 A KR 870011692A KR 870005153 A KR870005153 A KR 870005153A KR 870005153 A KR870005153 A KR 870005153A KR 870011692 A KR870011692 A KR 870011692A
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semiconductor device
device package
conductive
pad
fingers
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KR870005153A
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KR960004562B1 (ko
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아놀드 그린버그 로렌스
제이컵 랜도 데이비드
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엘리 와이스
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 장치 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발며의 일실시예에 따라 제조중의 한 단계에서 반도체 장치 패키지의 평면도.
제2도 및 3도는 상기와 동일한 실시예에 따라 다른 단계 제조중의 패키지의 부분적 파단 학대도.

Claims (10)

  1. 반도체 장치 패키지에 있어서, 장착 패드(41)와 패드의 측면 부근에 근접하게 가가의 한 단부를 갖는 다수의 제1전도성 핑거 및 그 사이에서 규정되는 제15간격(42)과 절연층(17)에서 형성되고 간격에 걸쳐 연장하는 다수의 제2전도성 핑거(16)를 구비하며, 상기 제2전도성 핑거(11)의 한 단부는 제1전도성 핑거에 결속되며 제2전도성 핑거의 반대 단부는 제1간격보다 적은 제2간격(40)을 규정하도록 패드의 측면부근에 가깝게 종단하는 것을 특징으로 하는 반도체 장치 패키지.
  2. 제1항에 있어서, 상기 장착 패드(41)에 결속된 하나의 주 표면 및 다수의 결속 패드(21)를 포함하는 그 반대의 주 표면의 두 개의 주 표면을 가지고 있는 반도체 장치(20)리 특징으로 하는 반도체 장치 패키지.
  3. 제2항에 있어서, 반도체 장치상의결속 패드와 대응 제2핑거 사이에서 전기적 도선 접속(22)을 특징으로 하는 반도체 장치 패키지.
  4. 제3항에 있어서, 상기 도선의 길이는 150밀(3.8mm)보다 짧은 것을 특징으로 하는 반도체 장치 패키지.
  5. 제3항에 있어서, 상기 패드와 제2전도성 핑거 사이의 전기적 접속 갯수는 한면당 적어도 15개인 것을 특징으로 하는 반도체 장치 패키지.
  6. 제1항에 있어서, 상기 제2전도성 핑거의 피치는 16밀(0.4mm)보다 적은 것을 특징으로 하는 반도체 장치 패키지.
  7. 제1항에 있어서, 전도성 패들(13)은 제1전도성 핑거(11)와 평면상에 형성되며 절연층(17)운 패들상에 만들어지는 것을 특징으로 하는 반도체 장치 패키지.
  8. 제7항에 있어서, 절연층을 홀(18)을 포함하며, 홀내에서 장착 패드는 상기 홀에 의해 노출된 기반 패들의 부분에 의해 규정되는 것을 특징으로 하는 반도체 장치 패키지.
  9. 항에 있어서, 장착 패드(제4도의30)는 제2전도성 핑거(16)와 동일하게 절연층(17)의 동일 표면에서 형성되는 것을 특징으로 하는 바도체 장치 패키지.
  10. 제1항에 있어서, 장착 패드는 네 개의 면을 가지고 있으며 각 면과 아주 가깝게 적어도 15개의 전도성 핑거가 있는 것을 특징으로 하는 바도체 장치 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870005153A 1986-05-27 1987-05-25 반도체 장치 패키지 KR960004562B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US866931 1986-05-27
US06/866,931 US4774635A (en) 1986-05-27 1986-05-27 Semiconductor package with high density I/O lead connection
US866,931 1992-04-10

Publications (2)

Publication Number Publication Date
KR870011692A true KR870011692A (ko) 1987-12-26
KR960004562B1 KR960004562B1 (ko) 1996-04-09

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US (1) US4774635A (ko)
EP (1) EP0247775B1 (ko)
JP (1) JP2671922B2 (ko)
KR (1) KR960004562B1 (ko)
AT (1) ATE95631T1 (ko)
CA (1) CA1252912A (ko)
DE (1) DE3787671T2 (ko)

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US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method

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DE3787671D1 (de) 1993-11-11
EP0247775A2 (en) 1987-12-02
KR960004562B1 (ko) 1996-04-09
EP0247775A3 (en) 1988-01-20
JP2671922B2 (ja) 1997-11-05
CA1252912A (en) 1989-04-18
DE3787671T2 (de) 1994-02-03
US4774635A (en) 1988-09-27
JPS6324647A (ja) 1988-02-02
EP0247775B1 (en) 1993-10-06
ATE95631T1 (de) 1993-10-15

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