KR940006083B1 - Loc 패키지 및 그 제조방법 - Google Patents

Loc 패키지 및 그 제조방법 Download PDF

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KR940006083B1
KR940006083B1 KR1019910015863A KR910015863A KR940006083B1 KR 940006083 B1 KR940006083 B1 KR 940006083B1 KR 1019910015863 A KR1019910015863 A KR 1019910015863A KR 910015863 A KR910015863 A KR 910015863A KR 940006083 B1 KR940006083 B1 KR 940006083B1
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inner lead
chip
forming
loc package
polymer
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KR1019910015863A
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KR930006867A (ko
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이희국
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금성일렉트론 주식회사
문정환
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Priority to KR1019910015863A priority Critical patent/KR940006083B1/ko
Priority to TW081106880A priority patent/TW301045B/zh
Priority to DE4230187A priority patent/DE4230187B4/de
Priority to US07/943,908 priority patent/US5742096A/en
Priority to JP04243295A priority patent/JP3121450B2/ja
Publication of KR930006867A publication Critical patent/KR930006867A/ko
Priority to US08/141,455 priority patent/US5358906A/en
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Publication of KR940006083B1 publication Critical patent/KR940006083B1/ko

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Abstract

내용 없음.

Description

LOC 패키지 및 그 제조방법
제1도는 종래 기술에 의한 LOC 패키지의 구조를 나타낸 종단면도.
제2도는 본 발명에 의한 LOC 패키지의 구조를 나타낸 종단면도.
제3도는 제 2 도의 "A"부 상세도.
제4도는 본 발명에 의한 LOC 패키지 제조공정에 있어서, 솔더링 공정을 나타낸 평면도.
제5도는 본 발명의 다른 실시예를 나타낸 종단면도.
* 도면의 주요부분에 대한 부호의 설명
11 : 칩 12 : 돌기
13 : 중합체 14 : 인너리드
15 : 패드 16 : 솔더
18 : 아우터리드
본 발명은 메모리 IC 패키징에 관한 것으로서, 특히 16M DRAM 이후의 메모리 패키지의 추세인 LOC(Lead-On Chip)(이하 "LOC"라 칭함) 타입패키지에 적당하도록 한 것이다.
베어 칩(Bare Chip)의 크기가 커짐에 따라 패키지의 리드 프레임을 확실하게 배치할 공간이 없어지게 되고, 이에 따라 리드프레임을 칩의 위에 올려 놓고 절연체인 폴리이마이드(polyimide)필름을 리드프레임과 칩 사이에 넣는 LOC 패키지 기술이 개발되고 있다.
그후 통상적인 와이어 본딩방법으로 리드 프레임과 칩을 전기적으로 상호 통하여 지도록 하고 있으며, 또한 다른 방법으로는 C-4 본딩이나 탭 본딩을 하게된다.
상기한 바와같은 기술을 첨부된 도면 제 1 도에 의거 상세히 설명하면 다음과 같다.
반도체 칩(1)의 상면 양측에 절연 물질인 폴리이마이드(2)가 일정 두께 각각 도포되고, 상기 반도체 칩(1)의 각 패드(3)와 프레임의 각 인너리드(4)는 와이어(5)에 의해 전기적으로 각각 접속되며, 상기 반도체 칩(1)과 프레임의 인너리드(4)를 포함하는 일정 면적이 에폭시(Epoxy)수지(6)로 몰딩된 구조로 되어 있다.
도면중 미설명 부호 7은 아우터리드(outer lead)을 나타낸 것이다.
이와같은 LOC 형태의 패키지는 프레임의 인너리드(4)를 반도체 칩(1)의 엑티브 셀(Ac-tive Cell)까지 끌어올려 프레임의 인너리드(4)가 패키지 내부에서 차지할 수 있는 범위를 크게 하였다는 장점을 가지게 된다.
그러나 상기한 바와같은 형태로 된 LOC 패키지는 리드프레임과 칩(1)사이에 비전도물질인 중합체(polymer)를 넣게되는데, 이 중합체와 리드프레임 그리고 리드프레임과 몰딩콤파운드와의 접착력이 문제가 되며 또한 이로 인해 각각의 인너리드(4)와 그 아래에 위치하는 회로 사이에 원하지 않는 와류 캐패시턴스(Parasitic Capacitance)가 생기게 되므로 이를 최대한 줄이기 위해서는 중합체의 두께를 두껍게 할수 밖에 없으며 이로인해 전체적으로 패키지의 두께가 두껍게 되는 결점을 가지게 된다.
본 발명은 종래의 이와같은 결점을 해결하기 위해 안출한 것으로서, 중합체의 두께를 줄이면서도 이들의 접착력을 향상시킬수 있도록 하는데 그 목적이 있다.
상기 목적을 본 발명의 형태에 따르면, 칩의 표면에 미세한 돌기를 형성하고 중합체와 인너리드의 상하방에는 요철면을 각각 형성하여 이들을 차례로 접합시켜서된 LOC 패키지가 제공된다.
또한 본 발명의 다른 형태에 따르면, 칩의 표면에 미세한 돌기를 형성하는 증착 공정과, 상기 돌기의 상부에 요철면을 가진 중합체를 형성하는 공정과, 상기 중합체의 요철면과 접속되게 인너리드에 요철면을 형성하는 공정과, 각 패드에 솔더를 형성하는 솔더공정과, 상기 솔더에 프레임의 각 인너리드를 솔더링하여 칩과 인너리드를 포함하는 일정 면적을 몰딩하는 몰딩공정과, 상기 몰딩된 패키지를 트리밍/포밍하는 공정으로 된 LOC 패키지의 제조 방법이 제공된다.
이하, 본 발명을 일실시예로 도시한 첨부된 도면 제 2 도 내지 제 4 도를 참고로 하여 더욱 상세히 설명하면 다음과 같다.
첨부도면 제 2 도는 본 발명에 의한 LOC 패키지의 구조를 나타낸 것이고 제 3 도는 제 2 도의 "A"부 상세도이고, 제 4 도는 본 발명에 의한 LOC 패키지 제조공정에 있어서 솔더링 공정을 나타낸 것이다.
본 발명의 LOC 패키지는 칩(11)의 상면 양측에 미세한 돌기(12)가 형성되고 그 상면에 형성된 중합체(13)와 인너리드(14)에는 요철면이 각각 형성되며 칩(11)의 각 패드(15)에는 솔더(16)가 형성된다.
또한 상기 인너리드(14)와 칩(11)의 각 패드(15)는 써모드(도시는 생략함)등에 의해 솔더링 되어 칩(11)과 인너리드(14)가 전기적으로 접속되고, 상기 칩(11)과 인너리드(14)를 포함하는 일정 면적이 에폭시 수지(17)로 일체 몰딩한 구조로 되어 있다.
이때 중합체(13)는 폴리이마이드 필름(유전 상수가 보통 3.5)을 쓸수도 있고 또는 대신에 테프론과 같은 플로로에틸렌계의 필름(Fluoro ethylene film : 유전상수가 2.0-2.2)을 사용하므로서 중합체(13)의 두께를 약 44% 정도 감소시킬수 있게 된다.
즉 종래의 중합체 두께가 대략 100μm 정도였으나 본 발명에서는 유전상수가 작기 때문에 60-70μm 정도로 하여도 와류 캐페시턴트가 커지지 않게된다.
그러나 테프론과 같은 플로로에틸렌 타입계 필름은 유전 상수가 작은 장점을 갖고 있으나 물질 자체의 약점인 점착 강도가 아주 낮기 때문에 이를 보완하기 위해 상하면에 아주 작은 요철면을 연속적으로 형성함과 동시에 인너리드(14)에도 아주 작은 요철면을 연속적으로 형성하여 접촉 면적을 증대시키도록 하였다.
또한 더욱더 접촉 면적을 증대시키기 위해 인너리드(14)에 일정 간격으로 통공을 형성하여 수지몰딩할 수도 있다.
상기한 바와같은 본 발명에 의한 LOC 패키지를 제조함에 있어서는 칩(11)의 표면에 미세한 돌기(12)를 저온에서 RF-스퍼터링(Sputtering)방법으로 약 400-500Å으로 증착하게 되는데, 이때 RF-스퍼터링을 Si3N4나 SiO2물질을 이용하게 된다.
그후 그 상면에 미세한 돌기(12)와 접속되게 요철면이 형성되도록 플로우에틸렌 필름으로 된 중합체(13)를 형성하는 공정을 수행하게 된다.
이와같이 미세한 돌기(12)에 중합체(13)의 형성이 완료되면 그 상면에 요철면을 가진 인너리드(14)를 중첩되게 접속시키게 되는데, 인너리드(14)에 요철면을 형성하는 방법을 좀더 구체적으로 설명하면 다음과 같다.
표면에 요철면이 형성된 로울러사이로 리드프레임에 형성된 인너리드를 통과시켜 요철면을 형성하거나 또는 고전류(100mA/cm2이상)를 이용한 전기도금법(electro plating)으로 작은 혹(nodule) 또는 수지상돌기(dendrite)형태의 요철면을 코팅하는 방법을 이용할수도 있다.
그후 각 칩(11)의 패드(15)에 솔더(16)를 형성하여 상기 솔더(16)에 프레임의 각 인너리드(14)를 솔더링하는데, 이때에는 첨부 도면 제 3 도의 제3(a)도에 나타낸 바와같이 일반적인 와이어(19) 본딩을 할수도 있지만 패키지의 전체적인 두께를 줄이기 위해 제3(b)도와 제3(c)도에 도시한 바와같이 TAB을 이용하거나 C-4 본딩을 이용하여 패드(15)와 직접 연결시킬수도 있다.
그러기 위해서는 제 4 도에 도시한 바와같이 접속부의 폭을 인너리드(14)폭보다 좁게 형성하여 상호 교호되게 설치하는 방법이 더욱 유리하게 된다.
그후 칩(11)과 인너리드(14)를 포함하는 일정 면적을 몰딩하는 몰딩공정을 수행한후 이를 트리밍/포밍하여 LOC 패키지를 얻게되는 것이다.
첨부도면 제 5 도는 본 발명의 다른 실시예를 나타낸 것으로서, 제5(a)도는 인너리드(14)와 아우터리드(18)를 별도로 형성하여 이들을 상호 솔더링한 것이고 제5(b)도는 테이프 아우터리드(18) 부분을 플레이팅하여 6-10mil 정도로 하므로서 기계적 강도를 얻을수 있게 한 것이다.
이상에서와 같이 본 발명은 칩(11)과 인너리드(14) 사이에 중합체(13)를 형성할때 이들이 상호 요철면에 의해 접속될수 있도록 하므로서, 기계적 강도를 더욱 향상시킬수 있게 됨은 물론 이로인해 중합체(13)의 두께를 더욱 얇게 할수 있게 되므로 패키지의 두께를 박형화할 수 있게 되는 효과를 가지게 된다.

Claims (10)

  1. 칩(11)과 인너리드(14)사이에 플로로 에틸렌계의 필름으로된 중합체(13)를 설치하고 인너리드와 아우터리드를 별도로 형성하여 본딩하여서 됨을 특징으로 하는 LOC 패키지.
  2. 제 1 항에 있어서, 중합체(13)의 두께를 60-70μm으로 하여서 된 LOC 패키지.
  3. 제 1 항에 있어서, 인너리드(14)와 아우터리드(18)를 탭 또는 C-4 본딩하여서 된 LOC 패키지.
  4. 제 1 항에 있어서, 칩(11)의 패드(15)에 접속되는 인너리드(14) 부분의 폭을 좁게하여 이들을 상호 교호되게 설치하여서 된 LOC 패키지.
  5. 제 1 항에 있어서, 인너리드(14)에 일정 간격으로 통공을 형성하여서 된 LOC 패키지.
  6. 칩(11)의 표면에 미세한 돌기(12)를 형성하는 증착 공정과, 상기 돌기(12)의 상부에 요철면을 가진 중합체(13)를 형성하는 공정과, 상기 중합체(13)의 요철면과 접속되게 인너리드(14)에 요철면을 형성하는 공정과, 상기 각 칩(11)의 패드(15)에 솔더(16)를 형성하는 솔더공정과, 상기 솔더(16)에 프레임의 각 인너리드(14)를 솔더링하여 칩(11)과 인너리드(14)를 포함하는 일정면적을 몰딩하는 몰딩공정과, 상기 몰딩된 패키지를 트리밍/포밍하는 공정을 포함하는 LOC 패키지 제조방법.
  7. 제 6 항에 있어서, 칩(11)의 표면에 형성된 미세한 돌기(12)를 저온에서 RF-스퍼터링 방법으로 형성하여서 된 LOC 패키지 제조방법.
  8. 제 6 항 또는 제 7 항에 있어서, 미세한 돌기(12)를 Si3N4나 SiO2를 하여서 된 LOC 패키지 제조방법.
  9. 제 6 항 또는 제 7 항에 있어서, 미세한 돌기(12)의 두께를 400-500Å으로 하여서 된 LOC 패키지 제조방법.
  10. 제 6 항에 있어서, 요철면을 가진 로울러를 이용하여 리드프레임의 인너리드(14)에 요철면을 형성하여서 된 LOC 패키지 제조방법.
KR1019910015863A 1991-09-11 1991-09-11 Loc 패키지 및 그 제조방법 KR940006083B1 (ko)

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KR1019910015863A KR940006083B1 (ko) 1991-09-11 1991-09-11 Loc 패키지 및 그 제조방법
TW081106880A TW301045B (ko) 1991-09-11 1992-08-31
DE4230187A DE4230187B4 (de) 1991-09-11 1992-09-09 Baueinheit mit Speicher-IC, sowie Verfahren zum Herstellen einer solchen Baueinheit
US07/943,908 US5742096A (en) 1991-09-11 1992-09-11 Lead on chip package
JP04243295A JP3121450B2 (ja) 1991-09-11 1992-09-11 Ｌｏｃパッケージおよびその製造方法
US08/141,455 US5358906A (en) 1991-09-11 1993-10-22 Method of making integrated circuit package containing inner leads with knurled surfaces

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JPH06169052A (ja) 1994-06-14
DE4230187A1 (de) 1993-03-18
JP3121450B2 (ja) 2000-12-25
US5742096A (en) 1998-04-21
US5358906A (en) 1994-10-25
KR930006867A (ko) 1993-04-22
DE4230187B4 (de) 2007-02-01

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