JPS55140238A - Tape carrier type semiconductor device - Google Patents

Tape carrier type semiconductor device

Info

Publication number
JPS55140238A
JPS55140238A JP4795479A JP4795479A JPS55140238A JP S55140238 A JPS55140238 A JP S55140238A JP 4795479 A JP4795479 A JP 4795479A JP 4795479 A JP4795479 A JP 4795479A JP S55140238 A JPS55140238 A JP S55140238A
Authority
JP
Japan
Prior art keywords
bonded
electrode
bump
lead
low load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4795479A
Other languages
Japanese (ja)
Inventor
Masami Kiyono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4795479A priority Critical patent/JPS55140238A/en
Publication of JPS55140238A publication Critical patent/JPS55140238A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE:To enable thermally pressure bonding of an inner lead to an electrode bump at low load by providing suitable ruggedness on the surface to be bonded of the bump and also on the surface to be bonded of the inner lead of a tape carrier type semiconductor device. CONSTITUTION:The surface to be bonded of an inner lead 2 secured onto a carrier tape 1 is formed with sawtooth ruggedness formed by etching on the surface to be bonded to the bump electrode 3 on a tape 4. The lead 2 is made of Cu and plated with Au, and the electrode 3 has Au surface. According to this configuration, the surface of the electrode 3 is initially point contacted with the surface of the lead to concentrate the contact load at the point contact portion. Therefore the point contact portion is readily deformed at low load and accordingly thermally pressure bonded at low load to obtain the bonded portion 5 having high rigidity and reliability. According to this method, Ni or Cu or the like can be used at plating inexpensively as compared with Au. Even in case of Au-Sn eutectic bonding system, it can prevent a shortcircuit owing to Au-Sn alloy flow-out.
JP4795479A 1979-04-20 1979-04-20 Tape carrier type semiconductor device Pending JPS55140238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4795479A JPS55140238A (en) 1979-04-20 1979-04-20 Tape carrier type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4795479A JPS55140238A (en) 1979-04-20 1979-04-20 Tape carrier type semiconductor device

Publications (1)

Publication Number Publication Date
JPS55140238A true JPS55140238A (en) 1980-11-01

Family

ID=12789738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4795479A Pending JPS55140238A (en) 1979-04-20 1979-04-20 Tape carrier type semiconductor device

Country Status (1)

Country Link
JP (1) JPS55140238A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200738A (en) * 1986-02-28 1987-09-04 Seiko Epson Corp Circuit substrate structure
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
JPH05175524A (en) * 1991-12-26 1993-07-13 Nec Corp Waveguide light receiving module
US5358906A (en) * 1991-09-11 1994-10-25 Gold Star Electron Co., Ltd. Method of making integrated circuit package containing inner leads with knurled surfaces
JPH06318649A (en) * 1993-04-30 1994-11-15 Hitachi Cable Ltd Semiconductor module substrate and semiconductor device using same
US5428889A (en) * 1991-09-09 1995-07-04 Hitachi Cable, Ltd. Method for manufacturing composite lead frame

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200738A (en) * 1986-02-28 1987-09-04 Seiko Epson Corp Circuit substrate structure
JPH0533533B2 (en) * 1986-02-28 1993-05-19 Seiko Epson Corp
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
US5428889A (en) * 1991-09-09 1995-07-04 Hitachi Cable, Ltd. Method for manufacturing composite lead frame
US5358906A (en) * 1991-09-11 1994-10-25 Gold Star Electron Co., Ltd. Method of making integrated circuit package containing inner leads with knurled surfaces
JPH05175524A (en) * 1991-12-26 1993-07-13 Nec Corp Waveguide light receiving module
JPH06318649A (en) * 1993-04-30 1994-11-15 Hitachi Cable Ltd Semiconductor module substrate and semiconductor device using same

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