JPS5645044A - Forming method for electrode lead - Google Patents

Forming method for electrode lead

Info

Publication number
JPS5645044A
JPS5645044A JP12116079A JP12116079A JPS5645044A JP S5645044 A JPS5645044 A JP S5645044A JP 12116079 A JP12116079 A JP 12116079A JP 12116079 A JP12116079 A JP 12116079A JP S5645044 A JPS5645044 A JP S5645044A
Authority
JP
Japan
Prior art keywords
eutectic
lead
projection
electrode lead
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12116079A
Other languages
Japanese (ja)
Other versions
JPS5946416B2 (en
Inventor
Kenzo Hatada
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12116079A priority Critical patent/JPS5946416B2/en
Publication of JPS5645044A publication Critical patent/JPS5645044A/en
Publication of JPS5946416B2 publication Critical patent/JPS5946416B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain an electrode lead having a higher reliability by preventing the production of a short-circuit and a crack in a semiconductor substrate due to the excess eutectic in a gang connection by means of Au-Sn eutectic. CONSTITUTION:A Cr-Cu film 12 is provided at the terminal position on a semiconductor substrate 11, and an Au projection 13 is formed on the film 12. The end of a Cu lead 15 provided on a polyimide resin film 14 is selectively plated with Sn 16. The length A of the Sn plating 16 is smaller than the length B of the Au projec- tion 13. The lead 15 is aligned with the Au projection 13 so that the Sn plating 16 is within the region of the Au projection 13, and pressed by means of a heated jig. On doing this, an Au-Sn eutectic 17 is formed, however there is no excess eutectic to flow out or down. Thus, a lead connection having a higher reliability is obtained.
JP12116079A 1979-09-19 1979-09-19 How to form electrode leads Expired JPS5946416B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12116079A JPS5946416B2 (en) 1979-09-19 1979-09-19 How to form electrode leads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12116079A JPS5946416B2 (en) 1979-09-19 1979-09-19 How to form electrode leads

Publications (2)

Publication Number Publication Date
JPS5645044A true JPS5645044A (en) 1981-04-24
JPS5946416B2 JPS5946416B2 (en) 1984-11-12

Family

ID=14804325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12116079A Expired JPS5946416B2 (en) 1979-09-19 1979-09-19 How to form electrode leads

Country Status (1)

Country Link
JP (1) JPS5946416B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596570A (en) * 1982-07-02 1984-01-13 Toshiba Corp Semiconductor device
JP2003298167A (en) * 2002-03-29 2003-10-17 Toshiba Corp Optical semiconductor device
JP2018074155A (en) * 2016-10-25 2018-05-10 ▲し▼創電子股▲ふん▼有限公司 Chip packaging structure and related inner lead bonding method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756771B2 (en) * 1988-06-27 1995-06-14 松下電工株式会社 Remote control relay

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596570A (en) * 1982-07-02 1984-01-13 Toshiba Corp Semiconductor device
JP2003298167A (en) * 2002-03-29 2003-10-17 Toshiba Corp Optical semiconductor device
JP2018074155A (en) * 2016-10-25 2018-05-10 ▲し▼創電子股▲ふん▼有限公司 Chip packaging structure and related inner lead bonding method

Also Published As

Publication number Publication date
JPS5946416B2 (en) 1984-11-12

Similar Documents

Publication Publication Date Title
FR2392758A1 (en) GOLD LAYER WELDING PROCESS
JPS57210638A (en) Hybrid integrated circuit
JPS5645044A (en) Forming method for electrode lead
JPS5586130A (en) Connection of semiconductor element
JPS54124678A (en) Lead frame
JPS5749252A (en) Manufacture of semiconductor device
JPS5645043A (en) Forming method for electrode lead
JPS55140238A (en) Tape carrier type semiconductor device
JPS56114358A (en) Semiconductor device and manufacture
JPS5718347A (en) Mounting structure of ic
JPH0233959A (en) Lead frame for semiconductor device
JPS57211762A (en) Lead frame for semiconductor
JPS5276875A (en) Semiconductor device
JPS56118385A (en) Semiconductor device
JPS56115550A (en) Manufacture of semiconductor device
JPS55121656A (en) Manufacture of semiconductor device
JPS54147781A (en) Manufacture for compound semicondutor device
JPS54126466A (en) Semiconductor device
JPS56135955A (en) Film carrier
JPS5591133A (en) Semiconductor device
JPS57192057A (en) Semiconductor device
JPS6471159A (en) Semiconductor device
JPS5413262A (en) Semiconductor device
JPS5448483A (en) Mounting method of semiconductor chip
JPS57164551A (en) Lead-frame for semiconductor device