JPS57210638A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS57210638A
JPS57210638A JP56094964A JP9496481A JPS57210638A JP S57210638 A JPS57210638 A JP S57210638A JP 56094964 A JP56094964 A JP 56094964A JP 9496481 A JP9496481 A JP 9496481A JP S57210638 A JPS57210638 A JP S57210638A
Authority
JP
Japan
Prior art keywords
conductor
bumps
electrode
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56094964A
Other languages
Japanese (ja)
Inventor
Toshio Hida
Tetsunori Sawae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56094964A priority Critical patent/JPS57210638A/en
Publication of JPS57210638A publication Critical patent/JPS57210638A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the deterioration in wettability between glass paste and an electrode conductor and in the solder wettability with the conductor by providing a suppressing member which eliminates the material of a connecting member to flow onto an electrode member when an element is connected to the connecting member. CONSTITUTION:An electrode conductor 12 is formed on an insulating substrate 11, and a polyimide resin film having preferable heat resistance is formed in the vicinity on the conductor 12 except the central part of the substance 11 and the part to be formed with solder bumps 14. Then, holes are opened at the terminal 31 of the conductor 12 and the part corresponding to the bumps 14, dams 13 are formed, and a flip chip IC15 is soldered through the bumps 14.
JP56094964A 1981-06-18 1981-06-18 Hybrid integrated circuit Pending JPS57210638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56094964A JPS57210638A (en) 1981-06-18 1981-06-18 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56094964A JPS57210638A (en) 1981-06-18 1981-06-18 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS57210638A true JPS57210638A (en) 1982-12-24

Family

ID=14124605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56094964A Pending JPS57210638A (en) 1981-06-18 1981-06-18 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS57210638A (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6300678B1 (en) 1997-10-03 2001-10-09 Fujitsu Limited I/O pin having solder dam for connecting substrates
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same
US8168525B2 (en) 2007-03-01 2012-05-01 Nec Corporation Electronic part mounting board and method of mounting the same

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5347162A (en) * 1989-08-28 1994-09-13 Lsi Logic Corporation Preformed planar structures employing embedded conductors
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5410805A (en) * 1989-08-28 1995-05-02 Lsi Logic Corporation Method and apparatus for isolation of flux materials in "flip-chip" manufacturing
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6452260B1 (en) 1997-09-02 2002-09-17 Silicon Light Machines Electrical interface to integrated circuit device having high density I/O count
US6300678B1 (en) 1997-10-03 2001-10-09 Fujitsu Limited I/O pin having solder dam for connecting substrates
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same
US8168525B2 (en) 2007-03-01 2012-05-01 Nec Corporation Electronic part mounting board and method of mounting the same

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